CSRNG Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	263.349us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	9.000s	33.672us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	13.472us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	42.000s	1.088ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	14.000s	368.379us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	138.512us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	13.472us	20	20	100.00
		csrng_csr_aliasing	14.000s	368.379us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	219.201us	194	200	97.00
V2	alerts	csrng_alert	1.133m	5.026ms	500	500	100.00
V2	err	csrng_err	4.000s	19.866us	497	500	99.40
V2	cmds	csrng_cmds	15.117m	70.148ms	49	50	98.00
V2	life cycle	csrng_cmds	15.117m	70.148ms	49	50	98.00
V2	stress_all	csrng_stress_all	31.833m	102.037ms	47	50	94.00
V2	intr_test	csrng_intr_test	13.000s	11.150us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	70.911us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	821.744us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	821.744us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	9.000s	33.672us	5	5	100.00
		csrng_csr_rw	8.000s	13.472us	20	20	100.00
		csrng_csr_aliasing	14.000s	368.379us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	149.289us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	9.000s	33.672us	5	5	100.00
		csrng_csr_rw	8.000s	13.472us	20	20	100.00
		csrng_csr_aliasing	14.000s	368.379us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	149.289us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	10.000s	941.903us	5	5	100.00
		csrng_tl_intg_err	11.000s	246.041us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	37.108us	50	50	100.00
		csrng_csr_rw	8.000s	13.472us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	5.026ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.833m	102.037ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	5.026ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.833m	102.037ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	5.026ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	246.041us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
		csrng_sec_cm	10.000s	941.903us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	219.201us	194	200	97.00
		csrng_err	4.000s	19.866us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.098h	139.992ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1607	1630	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 1.csrng_stress_all_with_rand_reset.90373292719228650364440082622109946680488498157886030921998961706549229935622
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 103753132 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 103753132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.86547630230538093858861146070513536405751498148712614216868040021001812431517
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6174615562 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6174615562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 5 failures:

Test csrng_intr has 5 failures.

0.csrng_intr.19245088934155715452034138096543070832134597450024685051982279884515008737892
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 22368397 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 22368397 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  22368397 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  22368397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

82.csrng_intr.69792390998624702574056339781820626208659360528514911247217127502926064433921
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/82.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 17835017 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 17835017 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  17835017 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  17835017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

13.csrng_err.73495293255828717213916597920464757940302372310973767543189221017558211342987
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  13.csrng_err.3347296907
  
  coverage files:
    model(design data) :  /workspace/coverage/default/13.csrng_err.3347296907/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/13.csrng_err.3347296907/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 09, 2024 at 16:57:18 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

269.csrng_err.16901380261047982371005928097463344676771622102838175681050881428452773353269
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/269.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  269.csrng_err.3869398837
  
  coverage files:
    model(design data) :  /workspace/coverage/default/269.csrng_err.3869398837/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/269.csrng_err.3869398837/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 09, 2024 at 17:02:17 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 0.csrng_stress_all_with_rand_reset.69375257975053084284979234490122227343542945100751346580257581612036920754081
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1381678766 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1381678766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.84095481362953406110453025628072131399129276949777850533403417360513610500341
    Line 442, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82569497674 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 82569497674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 12.csrng_stress_all.36280547172999276784028955836437341867255082455699384790614326749671709346675
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  22936538 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  22936538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.csrng_stress_all.30246151440721679366493007238451829384060796492450400663954369837695332355550
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3046910650 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3046910650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 7.csrng_stress_all_with_rand_reset.104411327404984375158012456236439674798422120161666218168178813850856202946028
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:cd6eb33c-0acb-4257-b16e-c430ea28bd4d
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 8.csrng_cmds.78400146282099841461258294016099184562530572640081988636669378013041369565803
    Line 366, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 13703232958 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (195492835312021788275163947519723088860 [0x93128cf074965789ff21daa454d2abdc] vs 0 [0x0])
  UVM_INFO @ 13703232958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 40.csrng_stress_all.31622656461383247282435394428900648911191467657379183985539907361362073937458
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 41883996201 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 41883996201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

120.csrng_intr.17439871992123150745775558770590813975933855683819548647978501946941841188548
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/120.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 10580875 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 10580875 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 10580875 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 10580875 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 10580875 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed