CSRNG Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	24.719us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	17.189us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	30.526us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	31.000s	638.215us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	140.021us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	12.000s	396.760us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	30.526us	20	20	100.00
		csrng_csr_aliasing	7.000s	140.021us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	323.881us	198	200	99.00
V2	alerts	csrng_alert	1.483m	7.584ms	500	500	100.00
V2	err	csrng_err	9.000s	130.600us	498	500	99.60
V2	cmds	csrng_cmds	15.000m	69.001ms	49	50	98.00
V2	life cycle	csrng_cmds	15.000m	69.001ms	49	50	98.00
V2	stress_all	csrng_stress_all	19.633m	37.943ms	46	50	92.00
V2	intr_test	csrng_intr_test	5.000s	151.413us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	217.118us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	24.000s	1.724ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	24.000s	1.724ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	17.189us	5	5	100.00
		csrng_csr_rw	4.000s	30.526us	20	20	100.00
		csrng_csr_aliasing	7.000s	140.021us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	86.991us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	17.189us	5	5	100.00
		csrng_csr_rw	4.000s	30.526us	20	20	100.00
		csrng_csr_aliasing	7.000s	140.021us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	86.991us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	6.000s	198.928us	5	5	100.00
		csrng_tl_intg_err	16.000s	775.572us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	78.229us	50	50	100.00
		csrng_csr_rw	4.000s	30.526us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.483m	7.584ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.633m	37.943ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.483m	7.584ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.633m	37.943ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.483m	7.584ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	775.572us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
		csrng_sec_cm	6.000s	198.928us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	323.881us	198	200	99.00
		csrng_err	9.000s	130.600us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.086h	39.978ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	98.26	95.90	98.89	96.48	91.90	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.15811047677447678068440125189103522099666712883598740411613724799503272972138
    Line 382, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25652587675 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25652587675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.88913440032029375529419948529889753024673689881149657693585177853749475647329
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51409338613 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51409338613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 2.csrng_stress_all.98021198278090319219089776619710573657656312386093063154669916760446256298167
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  40663222 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  40663222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.csrng_stress_all.85165188796211750666853884868442708620768115615829826724166248214642375079902
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  53509583 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  53509583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 5.csrng_stress_all_with_rand_reset.50364418706149201118058953151222958506852669306038270446535769670051915682725
    Line 409, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14929275858 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14929275858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.115604788437808087467938098062774334199475706816586833823433809108729683632919
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10993766099 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10993766099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

159.csrng_intr.113227801896551323447682401119370460679051886187783844252847820645350392327652
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/159.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 22075964 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 22075964 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 22075964 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 22075964 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  22075964 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

195.csrng_intr.59869801498857130866188818974110557603285181708728604998671373379655842383087
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/195.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 19103147 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 19103147 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  19103147 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  19103147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

270.csrng_err.36518385880047261420553959528124671653235624804670625182974504074816091482053
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/270.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  270.csrng_err.1183999941
  
  coverage files:
    model(design data) :  /workspace/coverage/default/270.csrng_err.1183999941/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/270.csrng_err.1183999941/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 10, 2024 at 18:11:19 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

314.csrng_err.25428818019955637383828865889453787374955013117036927465126744709419153653418
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/314.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  314.csrng_err.140672682
  
  coverage files:
    model(design data) :  /workspace/coverage/default/314.csrng_err.140672682/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/314.csrng_err.140672682/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 10, 2024 at 18:11:25 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 15.csrng_cmds.112146615327736118969360130711453240823753148599493053098284439424252471899571
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 2990191285 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (55622724220125023361966050763726007357 [0x29d88c09442f25380d4bd7c328462c3d] vs 0 [0x0])
  UVM_INFO @ 2990191285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```