CSRNG Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	54.424us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	59.754us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	76.116us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	25.000s	711.051us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	155.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	88.697us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	76.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	155.152us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	98.711us	196	200	98.00
V2	alerts	csrng_alert	1.083m	4.725ms	500	500	100.00
V2	err	csrng_err	14.000s	21.669us	499	500	99.80
V2	cmds	csrng_cmds	7.983m	43.684ms	49	50	98.00
V2	life cycle	csrng_cmds	7.983m	43.684ms	49	50	98.00
V2	stress_all	csrng_stress_all	41.650m	197.860ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	13.010us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	12.030us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	749.932us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	749.932us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	59.754us	5	5	100.00
		csrng_csr_rw	5.000s	76.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	155.152us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	210.718us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	59.754us	5	5	100.00
		csrng_csr_rw	5.000s	76.116us	20	20	100.00
		csrng_csr_aliasing	7.000s	155.152us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	210.718us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	7.000s	277.349us	5	5	100.00
		csrng_tl_intg_err	13.000s	613.826us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	39.961us	50	50	100.00
		csrng_csr_rw	5.000s	76.116us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	4.725ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	41.650m	197.860ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	4.725ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	41.650m	197.860ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	4.725ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	613.826us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
		csrng_sec_cm	7.000s	277.349us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	98.711us	196	200	98.00
		csrng_err	14.000s	21.669us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.063h	46.354ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.26	95.90	98.89	96.43	91.90	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.97791141326611803404876122759190904420103562618576138847951328106519041317084
    Line 286, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 613449298 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 613449298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.44056143999385684730013810137387286101436234757713754594124585713637269370321
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28047660128 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28047660128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

37.csrng_intr.64760223887363627949893199425430078534071105204009945053366667991665692994015
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 57347277 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 57347277 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  57347277 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  57347277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.csrng_intr.85175735895014815016224692123469354002793954029865021220620846898630593496413
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/50.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 27383177 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 27383177 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  27383177 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  27383177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 1.csrng_stress_all_with_rand_reset.43587077184579148330973538960894090348744575324791229806242309421652946177191
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2626976138 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2626976138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.48199595267268816458153626638514786238724524947503790910036286494442285055109
    Line 373, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28965815667 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28965815667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 41.csrng_stress_all.94521847008545573608733136401954240902838149537753099692709614992420087634932
    Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 28982920719 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 28982920719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 46.csrng_cmds.36038301662699033037080208820215242854488245085283166343841796807887106295672
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 5491759821 ps: (csrng_env_cfg.sv:288) [cfg] Check failed hw_v == v[app] (79389167988273228069402617099417556671 [0x3bb9cc2ec8971089a36a792e9cbc16bf] vs 0 [0x0])
  UVM_INFO @ 5491759821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

334.csrng_err.98835558134789930132110105998413255174809674364429295140297590237887382247678
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/334.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  334.csrng_err.2078890238
  
  coverage files:
    model(design data) :  /workspace/coverage/default/334.csrng_err.2078890238/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/334.csrng_err.2078890238/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 11, 2024 at 17:02:06 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1