CSRNG Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	91.443us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	35.026us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	58.945us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	418.355us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	158.618us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	192.002us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	58.945us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.618us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	9.000s	135.033us	195	200	97.50
V2	alerts	csrng_alert	1.283m	5.277ms	500	500	100.00
V2	err	csrng_err	5.000s	18.917us	496	500	99.20
V2	cmds	csrng_cmds	6.750m	15.459ms	50	50	100.00
V2	life cycle	csrng_cmds	6.750m	15.459ms	50	50	100.00
V2	stress_all	csrng_stress_all	16.733m	19.977ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	244.460us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	25.817us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	1.066ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	1.066ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	35.026us	5	5	100.00
		csrng_csr_rw	4.000s	58.945us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.618us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	402.271us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	35.026us	5	5	100.00
		csrng_csr_rw	4.000s	58.945us	20	20	100.00
		csrng_csr_aliasing	5.000s	158.618us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	402.271us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	7.000s	96.007us	5	5	100.00
		csrng_tl_intg_err	23.000s	448.261us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	13.469us	50	50	100.00
		csrng_csr_rw	4.000s	58.945us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.283m	5.277ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	16.733m	19.977ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.283m	5.277ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	16.733m	19.977ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.283m	5.277ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	448.261us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
		csrng_sec_cm	7.000s	96.007us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	135.033us	195	200	97.50
		csrng_err	5.000s	18.917us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	21.517m	54.926ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.02	98.14	95.64	98.71	96.48	91.84	100.00	96.78	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.20148865488069229664943337857343623960909971306455328662295140707666375977639
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9443284149 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9443284149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.86071568657859402365611317093160877403694826053847768421231215407185921191279
    Line 328, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29534781434 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 29534781434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed

has 5 failures:

Test csrng_intr has 5 failures.

19.csrng_intr.54282413998042190577383377139163025141331361329323656880227742650832718943079
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 135033148 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 135033148 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 135033148 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 135033148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

95.csrng_intr.58725097825926911997189162777638968014564559902497798454883677359489746916484
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/95.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 205075853 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 205075853 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 205075853 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 205075853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.59076446652862655462492953404581626180655957988110510867292878281511877973285
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1338583041 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1338583041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.65675728939398252592067480084625979287003775902744162404589899948783442977696
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22927589978 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22927589978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

78.csrng_err.14578289771835269576494118146107495130084196308148355543200732847094210028482
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/78.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  78.csrng_err.59827138
  
  coverage files:
    model(design data) :  /workspace/coverage/default/78.csrng_err.59827138/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/78.csrng_err.59827138/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 12, 2024 at 16:57:23 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

151.csrng_err.114600548420153507267578639080119336258932511946466812781141893604117029308664
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/151.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  151.csrng_err.2576337144
  
  coverage files:
    model(design data) :  /workspace/coverage/default/151.csrng_err.2576337144/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/151.csrng_err.2576337144/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 12, 2024 at 16:58:39 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 46.csrng_stress_all.26547684976872496139260153273201660438800320498448922182565969189052730148919
    Line 354, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 39979628956 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 39979628956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.csrng_stress_all.77189189428976133075310849936871581239576018528439624420071174906240791177669
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/47.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 9535550702 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 9535550702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```