CSRNG Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	172.335us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	15.646us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	181.352us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	35.000s	2.480ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	351.307us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	205.392us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	181.352us	20	20	100.00
		csrng_csr_aliasing	7.000s	351.307us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	341.423us	198	200	99.00
V2	alerts	csrng_alert	1.433m	6.550ms	500	500	100.00
V2	err	csrng_err	5.000s	25.203us	497	500	99.40
V2	cmds	csrng_cmds	10.817m	42.794ms	49	50	98.00
V2	life cycle	csrng_cmds	10.817m	42.794ms	49	50	98.00
V2	stress_all	csrng_stress_all	19.583m	29.531ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	126.306us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	96.780us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.251ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.251ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	15.646us	5	5	100.00
		csrng_csr_rw	5.000s	181.352us	20	20	100.00
		csrng_csr_aliasing	7.000s	351.307us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	248.804us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	15.646us	5	5	100.00
		csrng_csr_rw	5.000s	181.352us	20	20	100.00
		csrng_csr_aliasing	7.000s	351.307us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	248.804us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	12.000s	205.805us	5	5	100.00
		csrng_tl_intg_err	15.000s	489.142us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	99.269us	50	50	100.00
		csrng_csr_rw	5.000s	181.352us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.433m	6.550ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.583m	29.531ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.433m	6.550ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.583m	29.531ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.433m	6.550ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	489.142us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
		csrng_sec_cm	12.000s	205.805us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	341.423us	198	200	99.00
		csrng_err	5.000s	25.203us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	17.367m	22.014ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	98.21	95.79	98.81	96.59	91.84	100.00	97.14	90.42

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.95559374516126039724712958241744820791906129768765426834458673939357112121602
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3191073025 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3191073025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.80338096396659774737266122065110438600902682603238181771303577611517796198819
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4635507296 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4635507296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 1.csrng_stress_all_with_rand_reset.16739760965966243567726242735458696912754356915883426976245669165379494036619
    Line 407, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 22014272909 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 22014272909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.40858888427209246075544034380797545614176873559337574713572600485336522771656
    Line 287, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6541058445 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6541058445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

128.csrng_err.56737537824033605449636255730611989560616761432452973431417962587161622838341
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/128.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  128.csrng_err.1881504837
  
  coverage files:
    model(design data) :  /workspace/coverage/default/128.csrng_err.1881504837/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/128.csrng_err.1881504837/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 13, 2024 at 17:46:47 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

157.csrng_err.15603746615603780650022602758164795879086900415225801620119907546971416383252
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/157.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  157.csrng_err.3829223188
  
  coverage files:
    model(design data) :  /workspace/coverage/default/157.csrng_err.3829223188/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/157.csrng_err.3829223188/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 13, 2024 at 17:47:10 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

92.csrng_intr.107693472307773568061870909376840017189410149762722588907421757194895951110652
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/92.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 20056586 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 20056586 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  20056586 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  20056586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

156.csrng_intr.27455054097108600358190662276787547030598780979668069797786455674856266392302
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/156.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 77688276 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 77688276 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 77688276 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 77688276 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  77688276 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

UVM_FATAL (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 2.csrng_cmds.60851776711452825398918046137656419628694292375630546837488003487477926870732
    Line 401, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 1349010520 ps: (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (298945984038982371071048004912742562867 [0xe0e6e6f94c8112703ab7e34dd01a7c33] vs 0 [0x0])
  UVM_INFO @ 1349010520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 20.csrng_stress_all.82826860640785340036091357526720122315892580433448344950290618259186114547112
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 190469939 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 190469939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```