CSRNG Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	40.520us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	154.459us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	127.747us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	1.545ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	249.094us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	34.002us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	127.747us	20	20	100.00
		csrng_csr_aliasing	12.000s	249.094us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	57.790us	196	200	98.00
V2	alerts	csrng_alert	54.000s	3.920ms	500	500	100.00
V2	err	csrng_err	13.000s	19.857us	498	500	99.60
V2	cmds	csrng_cmds	9.933m	45.758ms	50	50	100.00
V2	life cycle	csrng_cmds	9.933m	45.758ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.533m	58.429ms	47	50	94.00
V2	intr_test	csrng_intr_test	13.000s	20.053us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	23.241us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	27.000s	1.646ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	27.000s	1.646ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	154.459us	5	5	100.00
		csrng_csr_rw	8.000s	127.747us	20	20	100.00
		csrng_csr_aliasing	12.000s	249.094us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	40.409us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	154.459us	5	5	100.00
		csrng_csr_rw	8.000s	127.747us	20	20	100.00
		csrng_csr_aliasing	12.000s	249.094us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	40.409us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	14.000s	33.693us	5	5	100.00
		csrng_tl_intg_err	21.000s	1.715ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	35.230us	50	50	100.00
		csrng_csr_rw	8.000s	127.747us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	54.000s	3.920ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.533m	58.429ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	54.000s	3.920ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.533m	58.429ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	54.000s	3.920ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	21.000s	1.715ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
		csrng_sec_cm	14.000s	33.693us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	57.790us	196	200	98.00
		csrng_err	13.000s	19.857us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	19.000m	87.784ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.23	95.85	98.84	96.65	91.90	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.95748569435648485453555729851651330275745781767193227137858886989718496647203
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 441002567 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 441002567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.72208339112929158596146603311765148511180980808266750395136771163372299954693
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3099522869 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3099522869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

41.csrng_intr.72635199031060811659080526679484830689581265586724134297247140796650760056686
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/41.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 17414277 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 17414277 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  17414277 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  17414277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

89.csrng_intr.95906295442430124435625522225213107652779222071110982906891556049599063651359
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 41896830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 41896830 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  41896830 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  41896830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 2.csrng_stress_all_with_rand_reset.9322638928277885103045397195889781554707786421774536021947349470594072689173
    Line 287, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131833344 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 131833344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.51135128321956730483094633762058263708132542621062735350924420622873017765042
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87784102373 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87784102373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 14.csrng_stress_all.79365244977168523202506533588348374561991207421019681482779468980558756643274
    Line 338, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 13058551057 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 13058551057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.csrng_stress_all.89329665128904031678238770538191290873817869388166398951563184935096742844715
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  16798530 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  16798530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

289.csrng_err.8215572145078088662092773739469231052369740051201455802864241723658445769744
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/289.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  289.csrng_err.1832373264
  
  coverage files:
    model(design data) :  /workspace/coverage/default/289.csrng_err.1832373264/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/289.csrng_err.1832373264/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 26, 2024 at 16:42:22 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

333.csrng_err.68832735609299030472184960339914856414212997191514829537532612263244537445736
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/333.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  333.csrng_err.371113320
  
  coverage files:
    model(design data) :  /workspace/coverage/default/333.csrng_err.371113320/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/333.csrng_err.371113320/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 26, 2024 at 16:42:33 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 6.csrng_stress_all.86226607243696820057152936315899172282747176176761161790432386316451038649122
    Line 366, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1994797646 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1994797646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```