CSRNG Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	12.000s	397.619us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	113.702us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	201.842us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	58.000s	3.694ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	163.234us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	400.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	201.842us	20	20	100.00
		csrng_csr_aliasing	7.000s	163.234us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	140.387us	200	200	100.00
V2	alerts	csrng_alert	1.317m	5.910ms	500	500	100.00
V2	err	csrng_err	14.000s	37.824us	499	500	99.80
V2	cmds	csrng_cmds	7.567m	37.280ms	50	50	100.00
V2	life cycle	csrng_cmds	7.567m	37.280ms	50	50	100.00
V2	stress_all	csrng_stress_all	24.350m	68.664ms	50	50	100.00
V2	intr_test	csrng_intr_test	8.000s	43.356us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	45.894us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	233.863us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	233.863us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	113.702us	5	5	100.00
		csrng_csr_rw	5.000s	201.842us	20	20	100.00
		csrng_csr_aliasing	7.000s	163.234us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	29.635us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	113.702us	5	5	100.00
		csrng_csr_rw	5.000s	201.842us	20	20	100.00
		csrng_csr_aliasing	7.000s	163.234us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	29.635us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	7.000s	590.554us	5	5	100.00
		csrng_tl_intg_err	19.000s	587.279us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	12.776us	50	50	100.00
		csrng_csr_rw	5.000s	201.842us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.317m	5.910ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.350m	68.664ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.317m	5.910ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.350m	68.664ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.317m	5.910ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	587.279us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
		csrng_sec_cm	7.000s	590.554us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	140.387us	200	200	100.00
		csrng_err	14.000s	37.824us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	54.433m	132.056ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1619	1630	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	98.28	95.95	98.91	96.70	91.90	100.00	97.32	90.53

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.52478281173174953663166814846191456153754434742939119373607151053013981824356
    Line 517, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132055683045 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 132055683045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.62489764461852031133546071855290503379921849245209204050300414006537098231956
    Line 304, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26155864924 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26155864924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 3.csrng_stress_all_with_rand_reset.25179045518192140392041103133667502546420009550290819822928742360012540615416
    Line 339, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18281771409 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18281771409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.71253816026787083835024936439779292094922319596133062142229047149849572491345
    Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7540643381 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7540643381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

261.csrng_err.19627470387442781846037325709953467604651720155032150258362381316247164555771
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/261.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  261.csrng_err.1778127355
  
  coverage files:
    model(design data) :  /workspace/coverage/default/261.csrng_err.1778127355/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/261.csrng_err.1778127355/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 27, 2024 at 16:43:34 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1