CSRNG Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	46.346us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	281.096us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	33.734us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	23.000s	522.330us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	347.798us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	282.434us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	33.734us	20	20	100.00
		csrng_csr_aliasing	10.000s	347.798us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	135.947us	198	200	99.00
V2	alerts	csrng_alert	1.100m	4.944ms	500	500	100.00
V2	err	csrng_err	18.000s	27.026us	497	500	99.40
V2	cmds	csrng_cmds	13.767m	50.442ms	50	50	100.00
V2	life cycle	csrng_cmds	13.767m	50.442ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.717m	63.136ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	92.825us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	76.178us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	978.721us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	978.721us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	281.096us	5	5	100.00
		csrng_csr_rw	4.000s	33.734us	20	20	100.00
		csrng_csr_aliasing	10.000s	347.798us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	79.018us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	281.096us	5	5	100.00
		csrng_csr_rw	4.000s	33.734us	20	20	100.00
		csrng_csr_aliasing	10.000s	347.798us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	79.018us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	9.000s	154.653us	5	5	100.00
		csrng_tl_intg_err	12.000s	530.739us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	55.141us	50	50	100.00
		csrng_csr_rw	4.000s	33.734us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.100m	4.944ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.717m	63.136ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.100m	4.944ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.717m	63.136ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.100m	4.944ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	530.739us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
		csrng_sec_cm	9.000s	154.653us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	135.947us	198	200	99.00
		csrng_err	18.000s	27.026us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	20.317m	50.668ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.23	95.85	98.86	96.48	91.84	100.00	97.32	90.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.93947883484594798349663210492636755212768324165148034840438195189440698995270
    Line 390, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7295832932 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7295832932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.26056394313578648959667405040294419562279939661230392121440389807796834987477
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27085014593 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27085014593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.115041141057139180474046722749047739197047256446884353106868575190762374911163
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4868067832 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4868067832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.91092001591320212516154258770062053006944158868485690050966695373886497255699
    Line 400, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50668477921 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 50668477921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

145.csrng_err.46388151425432294547358799038215205014986571926081551465335735842978302325141
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/145.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  145.csrng_err.531165589
  
  coverage files:
    model(design data) :  /workspace/coverage/default/145.csrng_err.531165589/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/145.csrng_err.531165589/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 28, 2024 at 16:47:49 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

146.csrng_err.5621107974064017030535916030790642499384992406462819280297564726059638318360
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/146.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  146.csrng_err.3911836952
  
  coverage files:
    model(design data) :  /workspace/coverage/default/146.csrng_err.3911836952/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/146.csrng_err.3911836952/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 28, 2024 at 16:47:41 PDT  (total: 00:00:12)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

15.csrng_intr.13503087316609968455748990457614459310316535533770564333105779232322539016163
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 31310126 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 31310126 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  31310126 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  31310126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

63.csrng_intr.113453704424564571626507400708631520630402679586734654838483887065447629376608
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/63.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 31219299 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 31219299 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  31219299 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  31219299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 4.csrng_stress_all.60014695824419410771873897157808087902804661942159010282957505442314906800653
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1002317954 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1002317954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 36.csrng_stress_all.95751299380587364330048573060320591981868632530492237974675485676385656728434
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2659264194 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2659264194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```