CSRNG Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	208.540us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	58.054us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	405.073us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	38.000s	2.958ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	264.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	24.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	405.073us	20	20	100.00
		csrng_csr_aliasing	9.000s	264.345us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	406.048us	200	200	100.00
V2	alerts	csrng_alert	1.133m	5.027ms	500	500	100.00
V2	err	csrng_err	5.000s	46.152us	496	500	99.20
V2	cmds	csrng_cmds	13.067m	77.121ms	50	50	100.00
V2	life cycle	csrng_cmds	13.067m	77.121ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.200m	76.775ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	145.303us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	203.337us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.162ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.162ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	58.054us	5	5	100.00
		csrng_csr_rw	7.000s	405.073us	20	20	100.00
		csrng_csr_aliasing	9.000s	264.345us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	368.709us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	58.054us	5	5	100.00
		csrng_csr_rw	7.000s	405.073us	20	20	100.00
		csrng_csr_aliasing	9.000s	264.345us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	368.709us	20	20	100.00
V2		TOTAL			1434	1440	99.58
V2S	tl_intg_err	csrng_sec_cm	5.000s	57.971us	5	5	100.00
		csrng_tl_intg_err	13.000s	478.346us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	12.952us	50	50	100.00
		csrng_csr_rw	7.000s	405.073us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	5.027ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.200m	76.775ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	5.027ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.200m	76.775ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	5.027ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	478.346us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
		csrng_sec_cm	5.000s	57.971us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	406.048us	200	200	100.00
		csrng_err	5.000s	46.152us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	24.600m	116.597ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1614	1630	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	98.23	95.85	98.86	96.48	91.84	100.00	97.32	89.89

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.91853418211208619740880580451558092399361952451338313840475886509616911680414
    Line 365, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27564655955 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27564655955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.19242009525837524312782876841763467750699890173927720798161058201982809221715
    Line 377, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7725814874 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7725814874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

26.csrng_err.63686176821911558567112634796611223743261802339755047854739785299055742805768
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  26.csrng_err.40625928
  
  coverage files:
    model(design data) :  /workspace/coverage/default/26.csrng_err.40625928/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/26.csrng_err.40625928/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 29, 2024 at 18:46:09 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

334.csrng_err.113579221028432240981368780991846683492564665606018118172533031399252582974250
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/334.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  334.csrng_err.1293927210
  
  coverage files:
    model(design data) :  /workspace/coverage/default/334.csrng_err.1293927210/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/334.csrng_err.1293927210/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 29, 2024 at 18:49:51 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 6.csrng_stress_all_with_rand_reset.38976718914982256217718725991994079504233785059271858470846711668095605718011
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116596946605 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 116596946605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.115789680016041763702061243563972498009148988412665954250709678154390741929712
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 102044231 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 102044231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 7.csrng_stress_all.47842054722728838835687109604466962848297204857842926090347325643359910534838
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2946328921 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2946328921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.csrng_stress_all.88732737767537148123924756544841692510342627764977861991603085289448519247779
    Line 366, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1862667957 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1862667957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 430.csrng_err.74755456612417025239612681466830661794605951196114975145699998183198375857879
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/430.csrng_err/latest/run.log
```
  UVM_ERROR @  13792348 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  13792348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```