CSRNG Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	21.000s	50.443us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.417m	15.118us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.500m	39.070us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	42.000s	477.646us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.700m	109.303us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.833m	30.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.500m	39.070us	20	20	100.00
		csrng_csr_aliasing	1.700m	109.303us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.567m	443.351us	200	200	100.00
V2	alerts	csrng_alert	2.617m	211.059us	500	500	100.00
V2	err	csrng_err	2.550m	20.463us	498	500	99.60
V2	cmds	csrng_cmds	9.483m	41.848ms	50	50	100.00
V2	life cycle	csrng_cmds	9.483m	41.848ms	50	50	100.00
V2	stress_all	csrng_stress_all	23.883m	62.065ms	47	50	94.00
V2	intr_test	csrng_intr_test	1.933m	65.534us	50	50	100.00
V2	alert_test	csrng_alert_test	19.000s	19.391us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	1.617m	78.633us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	1.617m	78.633us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.417m	15.118us	5	5	100.00
		csrng_csr_rw	1.500m	39.070us	20	20	100.00
		csrng_csr_aliasing	1.700m	109.303us	5	5	100.00
		csrng_same_csr_outstanding	1.333m	40.608us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.417m	15.118us	5	5	100.00
		csrng_csr_rw	1.500m	39.070us	20	20	100.00
		csrng_csr_aliasing	1.700m	109.303us	5	5	100.00
		csrng_same_csr_outstanding	1.333m	40.608us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	23.000s	196.303us	5	5	100.00
		csrng_tl_intg_err	2.017m	372.732us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	29.000s	10.723us	50	50	100.00
		csrng_csr_rw	1.500m	39.070us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.617m	211.059us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.883m	62.065ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.617m	211.059us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.883m	62.065ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.617m	211.059us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	2.017m	372.732us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
		csrng_sec_cm	23.000s	196.303us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.567m	443.351us	200	200	100.00
		csrng_err	2.550m	20.463us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.417m	5.147ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.34	98.37	96.16	99.09	96.65	91.84	100.00	97.32	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.88568337906509626814756198749654489470977421900481144792690561898174699841510
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1797608474 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1797608474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.107162770591042744908725791243150909557974086215252541776081815775721650857105
    Line 100, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 438359438 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 438359438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 14.csrng_stress_all.97802153346962522453488674674072645994857445751084934894688501751482040269943
    Line 150, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5293971514 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5293971514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.csrng_stress_all.87604866215672123113934221384254067901722106219065512303232679890838143688133
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1470458642 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1470458642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: *

has 2 failures:

Test csrng_err has 2 failures.

194.csrng_err.106338932819471249388561517206161441400139467001289411939692371817014495442133
Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/194.csrng_err/latest/run.log

  UVM_ERROR @  14668176 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  14668176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

367.csrng_err.4936625710717489015564919912220844174511646758664529941704949721995277517917
Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_03/csrng-sim-xcelium/367.csrng_err/latest/run.log

  UVM_ERROR @   6318646 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   6318646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---