CSRNG Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	190.445us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	130.704us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	211.587us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	39.000s	1.217ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	264.976us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	32.288us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	211.587us	20	20	100.00
		csrng_csr_aliasing	8.000s	264.976us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.783m	428.453us	197	200	98.50
V2	alerts	csrng_alert	2.600m	291.345us	500	500	100.00
V2	err	csrng_err	2.000m	34.096us	500	500	100.00
V2	cmds	csrng_cmds	8.600m	36.588ms	50	50	100.00
V2	life cycle	csrng_cmds	8.600m	36.588ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.350m	54.857ms	45	50	90.00
V2	intr_test	csrng_intr_test	5.000s	99.523us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	51.693us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	508.803us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	508.803us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	130.704us	5	5	100.00
		csrng_csr_rw	6.000s	211.587us	20	20	100.00
		csrng_csr_aliasing	8.000s	264.976us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	89.181us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	130.704us	5	5	100.00
		csrng_csr_rw	6.000s	211.587us	20	20	100.00
		csrng_csr_aliasing	8.000s	264.976us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	89.181us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	7.000s	119.860us	5	5	100.00
		csrng_tl_intg_err	16.000s	516.904us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	107.977us	50	50	100.00
		csrng_csr_rw	6.000s	211.587us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.600m	291.345us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.350m	54.857ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.600m	291.345us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.350m	54.857ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.600m	291.345us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	516.904us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
		csrng_sec_cm	7.000s	119.860us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.783m	428.453us	197	200	98.50
		csrng_err	2.000m	34.096us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.117m	3.548ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.29	98.35	96.11	99.07	96.70	91.77	100.00	97.14	90.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.18398945341389677751448680366612923977912203283712078209968828096075360330847
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2213217923 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2213217923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.49674131518629765974299377254252322379209099451698523329329584666191100636016
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2920235693 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2920235693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
- Test csrng_stress_all has 5 failures.
  - 12.csrng_stress_all.7140466777266250981993441479927111949979549989889971880616191772860194903446
    Line 170, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 37648168324 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 37648168324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.csrng_stress_all.55863394166267683168806730934923268134791038191243280103584213883924086515197
    Line 176, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 9671399233 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 9671399233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed

has 3 failures:

Test csrng_intr has 3 failures.

11.csrng_intr.29008385058592998269253160366348371726996483328452422063089018307539899435905
Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/11.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 51312041 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  51312041 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  51312041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.csrng_intr.98392694775719111438885387999344301960440123032865560786609826617523660991503
Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/25.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 369160932 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 369160932 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 369160932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.