CSRNG Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	342.278us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.083m	14.571us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.417m	35.411us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.950m	942.178us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.733m	40.324us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.800m	19.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.417m	35.411us	20	20	100.00
		csrng_csr_aliasing	1.733m	40.324us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	2.117m	77.259us	199	200	99.50
V2	alerts	csrng_alert	3.033m	177.066us	500	500	100.00
V2	err	csrng_err	2.300m	22.977us	500	500	100.00
V2	cmds	csrng_cmds	8.933m	25.524ms	50	50	100.00
V2	life cycle	csrng_cmds	8.933m	25.524ms	50	50	100.00
V2	stress_all	csrng_stress_all	33.467m	92.680ms	47	50	94.00
V2	intr_test	csrng_intr_test	1.750m	59.016us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	201.012us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	2.117m	141.085us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	2.117m	141.085us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.083m	14.571us	5	5	100.00
		csrng_csr_rw	1.417m	35.411us	20	20	100.00
		csrng_csr_aliasing	1.733m	40.324us	5	5	100.00
		csrng_same_csr_outstanding	1.567m	20.449us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.083m	14.571us	5	5	100.00
		csrng_csr_rw	1.417m	35.411us	20	20	100.00
		csrng_csr_aliasing	1.733m	40.324us	5	5	100.00
		csrng_same_csr_outstanding	1.567m	20.449us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	3.367m	3.497ms	5	5	100.00
		csrng_tl_intg_err	1.683m	132.773us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	154.486us	50	50	100.00
		csrng_csr_rw	1.417m	35.411us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	3.033m	177.066us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	33.467m	92.680ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	3.033m	177.066us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	33.467m	92.680ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	3.033m	177.066us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.683m	132.773us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
		csrng_sec_cm	3.367m	3.497ms	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	2.117m	77.259us	199	200	99.50
		csrng_err	2.300m	22.977us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.000m	4.042ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.33	98.37	96.16	99.09	96.70	91.84	100.00	97.32	90.65

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.2614292202564374274680525187529218975727136705942680984666356816489319937801
    Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1913085524 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1913085524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.86854996168245801196020914992926379039380447599821232467157415210883911184001
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 357037704 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 357037704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 4 failures:

Test csrng_stress_all_with_rand_reset has 4 failures.

1.csrng_stress_all_with_rand_reset.100864701329780869942130579280284220569366611236997612512516775206058821716638
Line 100, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  15714912 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  15714912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.csrng_stress_all_with_rand_reset.107298762596042219459253596125661976721488396884643643034197956352125684947554
Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   5427472 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @   5427472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 11.csrng_stress_all.105906592567176502882712581158962008911613337716847984576389765544232799016516
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  10609496 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  10609496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.csrng_stress_all.82771638693172584836678999406417791744662725246982195562378544666743907384573
    Line 164, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 12755887591 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 12755887591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed

has 1 failures:

Test csrng_intr has 1 failures.

50.csrng_intr.34645834616330307900590081636755179785481652812653226862782098836993565975198
Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/50.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 98752086 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  98752086 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  98752086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---