042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0.910s | 16.828us | 43 | 50 | 86.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.870s | 43.675us | 4 | 5 | 80.00 |
| V1 | csr_rw | edn_csr_rw | 0.990s | 26.490us | 15 | 20 | 75.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5.480s | 232.354us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.460s | 220.798us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 1.930s | 130.273us | 16 | 20 | 80.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.990s | 26.490us | 15 | 20 | 75.00 |
| edn_csr_aliasing | 1.460s | 220.798us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 84 | 105 | 80.00 | |||
| V2 | firmware | edn_genbits | 2.052m | 9.085ms | 261 | 300 | 87.00 |
| V2 | csrng_commands | edn_genbits | 2.052m | 9.085ms | 261 | 300 | 87.00 |
| V2 | genbits | edn_genbits | 2.052m | 9.085ms | 261 | 300 | 87.00 |
| V2 | interrupts | edn_intr | 1.170s | 19.650us | 40 | 50 | 80.00 |
| V2 | alerts | edn_alert | 1.100s | 17.427us | 43 | 50 | 86.00 |
| V2 | errs | edn_err | 1.380s | 32.669us | 88 | 100 | 88.00 |
| V2 | disable | edn_disable | 0.940s | 10.537us | 43 | 50 | 86.00 |
| edn_disable_auto_req_mode | 1.070s | 249.998us | 43 | 50 | 86.00 | ||
| V2 | stress_all | edn_stress_all | 4.240s | 198.153us | 44 | 50 | 88.00 |
| V2 | intr_test | edn_intr_test | 1.040s | 23.310us | 41 | 50 | 82.00 |
| V2 | alert_test | edn_alert_test | 1.020s | 66.025us | 39 | 50 | 78.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 3.280s | 105.486us | 14 | 20 | 70.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 3.280s | 105.486us | 14 | 20 | 70.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.870s | 43.675us | 4 | 5 | 80.00 |
| edn_csr_rw | 0.990s | 26.490us | 15 | 20 | 75.00 | ||
| edn_csr_aliasing | 1.460s | 220.798us | 4 | 5 | 80.00 | ||
| edn_same_csr_outstanding | 1.330s | 58.945us | 14 | 20 | 70.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.870s | 43.675us | 4 | 5 | 80.00 |
| edn_csr_rw | 0.990s | 26.490us | 15 | 20 | 75.00 | ||
| edn_csr_aliasing | 1.460s | 220.798us | 4 | 5 | 80.00 | ||
| edn_same_csr_outstanding | 1.330s | 58.945us | 14 | 20 | 70.00 | ||
| V2 | TOTAL | 670 | 790 | 84.81 | |||
| V2S | tl_intg_err | edn_sec_cm | 5.190s | 698.457us | 5 | 5 | 100.00 |
| edn_tl_intg_err | 15.020s | 1.085ms | 16 | 20 | 80.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 0.910s | 13.220us | 6 | 10 | 60.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.100s | 17.427us | 43 | 50 | 86.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 5.190s | 698.457us | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 5.190s | 698.457us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 5.190s | 698.457us | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.100s | 17.427us | 43 | 50 | 86.00 |
| edn_sec_cm | 5.190s | 698.457us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.100s | 17.427us | 43 | 50 | 86.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 15.020s | 1.085ms | 16 | 20 | 80.00 |
| V2S | TOTAL | 27 | 35 | 77.14 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 45.766m | 126.733ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 823 | 980 | 83.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 3 | 3 | 1 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.95 | 99.02 | 92.05 | 96.79 | 93.42 | 98.62 | 99.77 | 99.00 |
Exit reason: Error: User command failed Job returned non-zero exit code has 150 failures:
0.edn_stress_all.71909301372466845771493493888055981678698019206494644102094145654400681875783
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest/run.log
[make]: simulate
cd /workspace/0.edn_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991271239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.991271239
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.edn_stress_all.44744629864853797149532185179344883638702576181539514291081987160894463305836
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_stress_all/latest/run.log
[make]: simulate
cd /workspace/2.edn_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932028012 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1932028012
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
0.edn_stress_all_with_rand_reset.25370176354199103204485467194030574892258397743486103794369190338292423089733
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.edn_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714866757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3714866757
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
15.edn_stress_all_with_rand_reset.16641686735710543443783587732476369883084127007378574482816555752031958695438
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/15.edn_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444511246 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1444511246
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
0.edn_alert.26026554350222351510349350964860369729943360734856187067406066119559394678496
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_alert/latest/run.log
[make]: simulate
cd /workspace/0.edn_alert/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702863072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.702863072
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.edn_alert.29389309271410405646700993963749284990203511039595603899529367887098876534870
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_alert/latest/run.log
[make]: simulate
cd /workspace/1.edn_alert/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934265430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3934265430
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:40 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
0.edn_csr_bit_bash.62305259526353033733730189939436372323500765403500120876453615594000042135920
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.edn_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580779376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2580779376
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:31 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.edn_csr_bit_bash.98011408625712608602496577569383540605098751754086667155346054655634317084293
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/2.edn_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004452997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2004452997
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:29 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
1.edn_regwen.5536290315330612868042313359090803935175972646341159743855807403527122646428
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest/run.log
[make]: simulate
cd /workspace/1.edn_regwen/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699490716 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2699490716
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.edn_regwen.53676917328368090255739669508167104961201126913438119625741301767676309667896
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_regwen/latest/run.log
[make]: simulate
cd /workspace/2.edn_regwen/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597374520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1597374520
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more failures.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
Test edn_err has 1 failures.
10.edn_err.88327093437074019581052851062849991175614351969716453641511760650674015079390
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_err/latest/run.log
Job ID: smart:cbe58da2-2946-4b64-8c93-e7212f6bbd8d
Test edn_alert_test has 1 failures.
29.edn_alert_test.107080359662845341300897118193512974111816240515636282692132096436970980042114
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/29.edn_alert_test/latest/run.log
Job ID: smart:c901d17f-8ec0-4496-931b-49a837afa67e
Test edn_intr has 1 failures.
49.edn_intr.51247271833795766921972993826740194914619925357679291612805188667773736063635
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/49.edn_intr/latest/run.log
Job ID: smart:50cd85c5-02b5-4d9f-95dc-135a7a6384e3
Test edn_genbits has 1 failures.
73.edn_genbits.5428540467449631496647684035524698386355834674857403073813964072467339714570
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/73.edn_genbits/latest/run.log
Job ID: smart:008b8971-02fb-42fd-b481-89479edcbaf9
Job edn-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
Test edn_csr_mem_rw_with_rand_reset has 2 failures.
2.edn_csr_mem_rw_with_rand_reset.18255268600306584738950633374377525651042802433550269630010044740535629076738
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_csr_mem_rw_with_rand_reset/latest/run.log
Job ID: smart:ca5872d5-8268-4127-99d5-ea89b31dd5db
7.edn_csr_mem_rw_with_rand_reset.92767503031552410871380097976665240860411878824480751083577557758348766014693
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_csr_mem_rw_with_rand_reset/latest/run.log
Job ID: smart:4c899c93-5806-47d2-b191-d73518abe50d
Test edn_tl_errors has 1 failures.
11.edn_tl_errors.77863668722263881291712196332607914351828469657305328887547887572069715168724
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_tl_errors/latest/run.log
Job ID: smart:411d34d7-d4e4-45e1-9525-7bc654827d11