EDN Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.970s	14.990us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.920s	98.237us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	16.659us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.980s	1.701ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.540s	188.765us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.060s	397.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	16.659us	20	20	100.00
		edn_csr_aliasing	1.540s	188.765us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.960s	581.498us	300	300	100.00
V2	csrng_commands	edn_genbits	4.960s	581.498us	300	300	100.00
V2	genbits	edn_genbits	4.960s	581.498us	300	300	100.00
V2	interrupts	edn_intr	1.160s	20.780us	50	50	100.00
V2	alerts	edn_alert	1.050s	18.492us	50	50	100.00
V2	errs	edn_err	1.460s	18.182us	100	100	100.00
V2	disable	edn_disable	0.960s	14.043us	50	50	100.00
		edn_disable_auto_req_mode	1.150s	107.067us	50	50	100.00
V2	stress_all	edn_stress_all	4.510s	216.253us	50	50	100.00
V2	intr_test	edn_intr_test	0.900s	16.259us	50	50	100.00
V2	alert_test	edn_alert_test	1.050s	26.181us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.850s	110.352us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.850s	110.352us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.920s	98.237us	5	5	100.00
		edn_csr_rw	0.940s	16.659us	20	20	100.00
		edn_csr_aliasing	1.540s	188.765us	5	5	100.00
		edn_same_csr_outstanding	1.370s	36.414us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.920s	98.237us	5	5	100.00
		edn_csr_rw	0.940s	16.659us	20	20	100.00
		edn_csr_aliasing	1.540s	188.765us	5	5	100.00
		edn_same_csr_outstanding	1.370s	36.414us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	tl_intg_err	edn_sec_cm	5.720s	354.181us	5	5	100.00
		edn_tl_intg_err	2.770s	127.446us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.900s	72.630us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.050s	18.492us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.720s	354.181us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.720s	354.181us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.720s	354.181us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.050s	18.492us	50	50	100.00
		edn_sec_cm	5.720s	354.181us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.050s	18.492us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.770s	127.446us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.623m	415.847ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			979	980	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.04	99.02	92.46	96.79	93.42	98.62	99.77	99.20

Failure Buckets

• Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 29.edn_stress_all_with_rand_reset.24982862041943159412685336027433481009862561647100646606141307903436424611831
      Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/29.edn_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:86dcf884-e221-4d0e-b8c8-2c5005ed8486
      

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