EDN Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	23.307us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	18.192us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.920s	26.635us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.320s	997.265us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.440s	31.336us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.520s	59.877us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	26.635us	20	20	100.00
		edn_csr_aliasing	1.440s	31.336us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.230m	4.576ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.230m	4.576ms	300	300	100.00
V2	genbits	edn_genbits	1.230m	4.576ms	300	300	100.00
V2	interrupts	edn_intr	1.150s	20.366us	50	50	100.00
V2	alerts	edn_alert	1.060s	19.849us	50	50	100.00
V2	errs	edn_err	1.330s	29.745us	100	100	100.00
V2	disable	edn_disable	0.910s	13.204us	47	50	94.00
		edn_disable_auto_req_mode	1.130s	27.439us	50	50	100.00
V2	stress_all	edn_stress_all	4.260s	782.077us	50	50	100.00
V2	intr_test	edn_intr_test	0.920s	18.876us	50	50	100.00
V2	alert_test	edn_alert_test	1.180s	71.913us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.280s	568.688us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.280s	568.688us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	18.192us	5	5	100.00
		edn_csr_rw	0.920s	26.635us	20	20	100.00
		edn_csr_aliasing	1.440s	31.336us	5	5	100.00
		edn_same_csr_outstanding	1.490s	145.290us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	18.192us	5	5	100.00
		edn_csr_rw	0.920s	26.635us	20	20	100.00
		edn_csr_aliasing	1.440s	31.336us	5	5	100.00
		edn_same_csr_outstanding	1.490s	145.290us	20	20	100.00
V2		TOTAL			787	790	99.62
V2S	tl_intg_err	edn_sec_cm	15.530s	1.106ms	5	5	100.00
		edn_tl_intg_err	12.750s	3.476ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.000s	15.838us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	19.849us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	15.530s	1.106ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	15.530s	1.106ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	15.530s	1.106ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	19.849us	50	50	100.00
		edn_sec_cm	15.530s	1.106ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	19.849us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	12.750s	3.476ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	41.754m	521.724ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			976	980	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	99.02	92.39	96.79	92.11	98.62	99.77	98.19

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_disable has 2 failures.

    • 33.edn_disable.5787848288773296155869974623722018235332990977950859878717972068784395879835
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.edn_disable.109199912881724474223167905788230141692874166804013401849939209928450212702848
      Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/36.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test edn_disable has 1 failures.

    • 21.edn_disable.70101547839427646138748946200550778765100452917277045454142783343154368022011
      Line 256, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/21.edn_disable/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'h0000ffff) == (exp_vals[4] & 'h0000ffff)))'
        UVM_ERROR @   1872499 ps: (edn_csr_assert_fpv.sv:188) [ASSERT FAILED] ctrl_rd_A
        UVM_INFO @   1872499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 41.edn_stress_all_with_rand_reset.10923105978514623037190586381353337059195941547662149060087990708034316602794
      Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/41.edn_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:25ea9f7e-d7e3-426d-b67b-7ffb2b00974b
      

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