EDN Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.010s	21.514us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.960s	41.132us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	12.791us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.340s	521.506us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.180s	28.712us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.810s	93.566us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	12.791us	20	20	100.00
		edn_csr_aliasing	1.180s	28.712us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.241m	9.558ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.241m	9.558ms	300	300	100.00
V2	genbits	edn_genbits	2.241m	9.558ms	300	300	100.00
V2	interrupts	edn_intr	1.200s	21.277us	50	50	100.00
V2	alerts	edn_alert	1.060s	19.472us	50	50	100.00
V2	errs	edn_err	1.350s	33.641us	100	100	100.00
V2	disable	edn_disable	0.940s	14.505us	49	50	98.00
		edn_disable_auto_req_mode	1.210s	126.755us	50	50	100.00
V2	stress_all	edn_stress_all	4.540s	213.001us	50	50	100.00
V2	intr_test	edn_intr_test	0.900s	20.705us	50	50	100.00
V2	alert_test	edn_alert_test	1.140s	59.099us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.280s	123.372us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.280s	123.372us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.960s	41.132us	5	5	100.00
		edn_csr_rw	1.010s	12.791us	20	20	100.00
		edn_csr_aliasing	1.180s	28.712us	5	5	100.00
		edn_same_csr_outstanding	1.420s	35.718us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.960s	41.132us	5	5	100.00
		edn_csr_rw	1.010s	12.791us	20	20	100.00
		edn_csr_aliasing	1.180s	28.712us	5	5	100.00
		edn_same_csr_outstanding	1.420s	35.718us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	tl_intg_err	edn_sec_cm	7.000s	1.036ms	5	5	100.00
		edn_tl_intg_err	8.420s	512.346us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.930s	15.241us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	19.472us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.000s	1.036ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.000s	1.036ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.000s	1.036ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	19.472us	50	50	100.00
		edn_sec_cm	7.000s	1.036ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	19.472us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	8.420s	512.346us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	47.300m	461.701ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			979	980	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.62	99.02	92.32	96.79	91.45	98.62	99.77	98.39

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test edn_disable has 1 failures.

    • 30.edn_disable.88704109363432113518247088682501508601887490818750721460874838278367640503557
      Line 256, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/30.edn_disable/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'h0000ffff) == (exp_vals[4] & 'h0000ffff)))'
        UVM_ERROR @   5107762 ps: (edn_csr_assert_fpv.sv:188) [ASSERT FAILED] ctrl_rd_A
        UVM_INFO @   5107762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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