EDN Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.960s	14.085us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	102.032us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	16.359us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.930s	1.553ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.510s	89.902us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.830s	54.850us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	16.359us	20	20	100.00
		edn_csr_aliasing	1.510s	89.902us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	48.496m	200.000ms	258	300	86.00
V2	csrng_commands	edn_genbits	48.496m	200.000ms	258	300	86.00
V2	genbits	edn_genbits	48.496m	200.000ms	258	300	86.00
V2	interrupts	edn_intr	1.240s	19.700us	50	50	100.00
V2	alerts	edn_alert	1.060s	123.337us	50	50	100.00
V2	errs	edn_err	1.460s	34.938us	86	100	86.00
V2	disable	edn_disable	2.070s	100.000us	49	50	98.00
		edn_disable_auto_req_mode	1.830s	500.000us	49	50	98.00
V2	stress_all	edn_stress_all	4.350s	1.261ms	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	18.777us	50	50	100.00
V2	alert_test	edn_alert_test	1.730s	70.733us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.390s	1.077ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.390s	1.077ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	102.032us	5	5	100.00
		edn_csr_rw	0.960s	16.359us	20	20	100.00
		edn_csr_aliasing	1.510s	89.902us	5	5	100.00
		edn_same_csr_outstanding	1.570s	475.368us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	102.032us	5	5	100.00
		edn_csr_rw	0.960s	16.359us	20	20	100.00
		edn_csr_aliasing	1.510s	89.902us	5	5	100.00
		edn_same_csr_outstanding	1.570s	475.368us	20	20	100.00
V2		TOTAL			732	790	92.66
V2S	tl_intg_err	edn_sec_cm	6.870s	468.531us	5	5	100.00
		edn_tl_intg_err	4.290s	517.599us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.940s	20.812us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	123.337us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.870s	468.531us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.870s	468.531us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.870s	468.531us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	123.337us	50	50	100.00
		edn_sec_cm	6.870s	468.531us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	123.337us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.290s	517.599us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	57.385m	242.592ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			922	980	94.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	7	63.64
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	99.02	92.31	96.74	87.34	98.48	99.77	98.34

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 21 failures:
- Test edn_disable has 1 failures.
  - 7.edn_disable.21675590896904395063047733914517230902829566482233023599990876418875368581075
    Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable/latest/run.log
```
  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test edn_genbits has 19 failures.
  - 18.edn_genbits.69384583402419544680719682559468680188633460626324985085850613415101588576299
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/18.edn_genbits/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.edn_genbits.115350232826149623188099794146442147960230714143281360443405253090662802368299
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_genbits/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
- Test edn_disable_auto_req_mode has 1 failures.
  - 34.edn_disable_auto_req_mode.97669078348753789845329583300737603935666626832820608619552885358530235788737
    Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/34.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 14 failures:

Test edn_err has 13 failures.

24.edn_err.7918366913695175309278771421435751351739245484747575119687933760866771854469
Line 297, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/24.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4545881 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

48.edn_err.93109391010755282955439060423021625461761261210961743955617978821292480891433
Line 297, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/48.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 20037990 ps, Illegal
    state bin il of coverpoint csrng_cmd_cp in covergroup

... and 11 more failures.

Test edn_genbits has 1 failures.

144.edn_genbits.27506703527059621834368043297051036182244112521103458502569422493908163670411
Line 254, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/144.edn_genbits/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2359436 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

UVM_FATAL (edn_scoreboard.sv:466) [scoreboard] Check failed (instantiated) Generate command not allowed without instantiated CSRNG instance. cmd: * has 10 failures:

Test edn_genbits has 10 failures.

11.edn_genbits.32619339320429142998847917279546014044594339698477950139534027087444429555957
Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_genbits/latest/run.log

  UVM_FATAL @   3497211 ps: (edn_scoreboard.sv:466) [uvm_test_top.env.scoreboard] Check failed (instantiated) Generate command not allowed without instantiated CSRNG instance. cmd: 0x00013663
  UVM_INFO @   3497211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.edn_genbits.44697436018239246520117550240915537690774130107536097207625837814275175302520
Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/37.edn_genbits/latest/run.log

  UVM_FATAL @   2395921 ps: (edn_scoreboard.sv:466) [uvm_test_top.env.scoreboard] Check failed (instantiated) Generate command not allowed without instantiated CSRNG instance. cmd: 0x00009903
  UVM_INFO @   2395921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.intr_state.edn_cmd_req_done (addr=*) == * has 8 failures:
- Test edn_genbits has 8 failures.
  - 94.edn_genbits.41544286356497758661453313129757641248816668462087371580729658172767226064691
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/94.edn_genbits/latest/run.log
```
  UVM_FATAL @ 10005081906 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.intr_state.edn_cmd_req_done (addr=0x442b3580) == 0x1
  UVM_INFO @ 10005081906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 105.edn_genbits.63071000842769786514266191412934633881154423220621889151825024133242194716460
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/105.edn_genbits/latest/run.log
```
  UVM_FATAL @ 10005084740 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.intr_state.edn_cmd_req_done (addr=0x55119d00) == 0x1
  UVM_INFO @ 10005084740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (edn_scoreboard.sv:535) [scoreboard] Check failed (instantiated) Uninstantiate command not allowed without instantiated CSRNG instance. cmd: * has 1 failures:
- Test edn_genbits has 1 failures.
  - 39.edn_genbits.63020335761629477696099820080235495244216986703240797514897559742358269981017
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/39.edn_genbits/latest/run.log
```
  UVM_FATAL @  33373539 ps: (edn_scoreboard.sv:535) [uvm_test_top.env.scoreboard] Check failed (instantiated) Uninstantiate command not allowed without instantiated CSRNG instance. cmd: 0xc0602b1d
  UVM_INFO @  33373539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$stable(h_data)' has 1 failures:
- Test edn_err has 1 failures.
  - 45.edn_err.99653910438775889776856386138303703891717726802253382043265139170133027434162
    Line 297, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/45.edn_err/latest/run.log
```
      Offending '$stable(h_data)'
  UVM_ERROR @   2535982 ps: (push_pull_if.sv:120) [ASSERT FAILED] H_DataStableWhenValidAndNotReady_A
  UVM_INFO @   2535982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (edn_scoreboard.sv:567) scoreboard [scoreboard] Invalid application command. cmd: * has 1 failures:
- Test edn_genbits has 1 failures.
  - 51.edn_genbits.70348221740314485611141382055078764958213138245069893500122118837663582732990
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/51.edn_genbits/latest/run.log
```
  UVM_ERROR @   7446318 ps: (edn_scoreboard.sv:567) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid application command. cmd: 0x7b474717
  UVM_INFO @   7446318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=*) == * has 1 failures:
- Test edn_genbits has 1 failures.
  - 53.edn_genbits.47882583957109838646069145228298268186668638849271325184812953475483488768466
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/53.edn_genbits/latest/run.log
```
  UVM_FATAL @ 10069050191 ps: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=0x2bff48c0) == 0xc1
  UVM_INFO @ 10069050191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Instantiate command * in sw mode has to match the value in sw_cmd_req register *. has 1 failures:
- Test edn_genbits has 1 failures.
  - 147.edn_genbits.15721002736071546365872787280839421197539882549501031333838537275181380284757
    Line 253, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/147.edn_genbits/latest/run.log
```
  UVM_FATAL @   7567998 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Instantiate command 0x6d7cdca1 in sw mode has to match the value in sw_cmd_req register 0x0000e6b1.
  UVM_INFO @   7567998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```