EDN Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.000s	29.890us	49	50	98.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	19.293us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.940s	13.557us	19	20	95.00
V1	csr_bit_bash	edn_csr_bit_bash	5.760s	228.615us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	72.213us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.000s	138.823us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.940s	13.557us	19	20	95.00
		edn_csr_aliasing	1.420s	72.213us	4	5	80.00
V1		TOTAL			101	105	96.19
V2	firmware	edn_genbits	9.240s	1.332ms	299	300	99.67
V2	csrng_commands	edn_genbits	9.240s	1.332ms	299	300	99.67
V2	genbits	edn_genbits	9.240s	1.332ms	299	300	99.67
V2	interrupts	edn_intr	1.240s	30.370us	49	50	98.00
V2	alerts	edn_alert	1.070s	19.521us	49	50	98.00
V2	errs	edn_err	1.340s	29.212us	91	100	91.00
V2	disable	edn_disable	0.930s	14.886us	49	50	98.00
		edn_disable_auto_req_mode	1.700s	500.000us	44	50	88.00
V2	stress_all	edn_stress_all	5.670s	2.841ms	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	12.599us	49	50	98.00
V2	alert_test	edn_alert_test	2.680s	133.536us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.470s	458.552us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.470s	458.552us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	19.293us	5	5	100.00
		edn_csr_rw	0.940s	13.557us	19	20	95.00
		edn_csr_aliasing	1.420s	72.213us	4	5	80.00
		edn_same_csr_outstanding	1.510s	154.059us	19	20	95.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	19.293us	5	5	100.00
		edn_csr_rw	0.940s	13.557us	19	20	95.00
		edn_csr_aliasing	1.420s	72.213us	4	5	80.00
		edn_same_csr_outstanding	1.510s	154.059us	19	20	95.00
V2		TOTAL			769	790	97.34
V2S	tl_intg_err	edn_sec_cm	6.790s	3.055ms	5	5	100.00
		edn_tl_intg_err	4.170s	219.661us	19	20	95.00
V2S	sec_cm_config_regwen	edn_regwen	0.980s	14.361us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.070s	19.521us	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.790s	3.055ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.790s	3.055ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.790s	3.055ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.070s	19.521us	49	50	98.00
		edn_sec_cm	6.790s	3.055ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.070s	19.521us	49	50	98.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.170s	219.661us	19	20	95.00
V2S		TOTAL			34	35	97.14
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	45.977m	208.824ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			954	980	97.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	2	33.33
V2	11	11	3	27.27
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.65	98.70	91.81	96.79	89.24	97.62	96.60	98.78

Failure Buckets

Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 9 failures:

Test edn_err has 9 failures.

8.edn_err.51778987400450564194415340999342062830448885871311767175493639448907609904075
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 7980191 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

12.edn_err.19992796661573840489867122035912151320051900963310105721852369048978202550345
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/12.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4247531 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

... and 7 more failures.

UVM_ERROR (edn_scoreboard.sv:270) [scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (* [*] vs * [*]) has 4 failures:
- Test edn_disable_auto_req_mode has 4 failures.
  - 2.edn_disable_auto_req_mode.68619296384816342396792931615900628761115626341948642630450073844441211387076
    Line 260, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @   9456769 ps: (edn_scoreboard.sv:270) [uvm_test_top.env.scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (1 [0x1] vs 0 [0x0])
  UVM_INFO @   9456769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.edn_disable_auto_req_mode.46098730829352121555390060509728656668551346504684474512330396095267022269280
    Line 260, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/3.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  25698630 ps: (edn_scoreboard.sv:270) [uvm_test_top.env.scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (1 [0x1] vs 0 [0x0])
  UVM_INFO @  25698630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Job edn-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 3 failures:
- Test edn_csr_aliasing has 1 failures.
  - 0.edn_csr_aliasing.107628395764699069175599476371853981032311289918674679544945636275254430512380
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_csr_aliasing/latest/run.log
```
  Job ID: smart:cd864685-a7e8-4cd0-8247-ef166cb17172
```
- Test edn_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.edn_csr_mem_rw_with_rand_reset.20032105449543659729067727535958717508454309845447000760193118150092102638009
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_csr_mem_rw_with_rand_reset/latest/run.log
```
  Job ID: smart:73081f9c-974a-4419-a4d5-b24215ace84f
```
- Test edn_tl_intg_err has 1 failures.
  - 8.edn_tl_intg_err.104969192299775663574321339972512361367231742312025063637552961221534318962739
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_tl_intg_err/latest/run.log
```
  Job ID: smart:51659ae6-1b6e-40d8-b85a-dd8114c2000d
```
Job edn-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test edn_same_csr_outstanding has 1 failures.
  - 10.edn_same_csr_outstanding.18093397033074666888763481024535586716109534970069081530819931183206906281166
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/10.edn_same_csr_outstanding/latest/run.log
```
  Job ID: smart:bce8abeb-641c-4679-b547-105d48051021
```
- Test edn_intr_test has 1 failures.
  - 49.edn_intr_test.105769687409797836921271073673519782456657134361932942962768804752102648281403
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/49.edn_intr_test/latest/run.log
```
  Job ID: smart:64724534-376c-4669-bd25-b9c9c88ddd9d
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_disable_auto_req_mode has 2 failures.
  - 33.edn_disable_auto_req_mode.24359523548997266269371683529878276256729484460970886857550130018918719844834
    Line 257, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.edn_disable_auto_req_mode.69926528115700175469788826028690985600200915836209255784527580359806529655020
    Line 257, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/34.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job edn-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test edn_csr_rw has 1 failures.
  - 1.edn_csr_rw.8029794030895403483424748352764620548232981572409951942401279730065432357932
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_csr_rw/latest/run.log
```
  Job ID: smart:661c77f1-dbec-433d-ad5f-0612dfa77440
```
Job edn-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test edn_smoke has 1 failures.
  - 9.edn_smoke.16341629081120269088514555808919016078696902830664524854223215328476877773715
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/9.edn_smoke/latest/run.log
```
  Job ID: smart:95a42c31-29ba-4455-949c-ac1024bf2d11
```
Job edn-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test edn_intr has 1 failures.
  - 20.edn_intr.73512303528525684529195440426281208024258574580557062875881324079136258107841
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/20.edn_intr/latest/run.log
```
  Job ID: smart:439d8de4-a0f4-4d7c-bdde-89e98d915350
```
Job edn-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test edn_genbits has 1 failures.
  - 32.edn_genbits.40490245840910475376332299048050237084047586597966844396387585751545758544502
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/32.edn_genbits/latest/run.log
```
  Job ID: smart:19f627bd-51d2-41b8-b510-73bb9cd893bf
```
UVM_ERROR (edn_scoreboard.sv:322) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.ctrl has 1 failures:
- Test edn_disable has 1 failures.
  - 42.edn_disable.60598566755119836811400562587345263002711715341017962030178837048832159498275
    Line 257, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/42.edn_disable/latest/run.log
```
  UVM_ERROR @   8334341 ps: (edn_scoreboard.sv:322) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (39270 [0x9966] vs 39273 [0x9969]) reg name: edn_reg_block.ctrl
  UVM_INFO @   8334341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job edn-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test edn_alert has 1 failures.
  - 48.edn_alert.2314800356912131164595195399492756213776135841153140294335063528355323319413
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/48.edn_alert/latest/run.log
```
  Job ID: smart:3fcd1644-c0d0-474c-a2c9-e88420555d68
```