4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 20 | 0.00 | ||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | firmware | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | csrng_commands | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | genbits | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | interrupts | edn_intr | 0 | 50 | 0.00 | ||
| V2 | alerts | edn_alert | 0 | 50 | 0.00 | ||
| V2 | errs | edn_err | 0 | 100 | 0.00 | ||
| V2 | disable | edn_disable | 0 | 50 | 0.00 | ||
| edn_disable_auto_req_mode | 0 | 50 | 0.00 | ||||
| V2 | stress_all | edn_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | edn_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 790 | 0.00 | |||
| V2S | tl_intg_err | edn_sec_cm | 0 | 5 | 0.00 | ||
| edn_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 0 | 10 | 0.00 | ||
| V2S | sec_cm_config_mubi | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0 | 50 | 0.00 | ||
| edn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 35 | 0.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 980 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 982 failures:
0.edn_smoke.60620178276509286417864270991818546002791209559307971152517300102606117284854
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_smoke/latest/run.log
1.edn_smoke.111074338305209535718362704262303820229919780777143063745024224330819995684185
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_smoke/latest/run.log
... and 48 more failures.
0.edn_regwen.95429348896575398494692396757950732309587483536217536717110775729384327704464
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_regwen/latest/run.log
1.edn_regwen.107286984177230748653229159790605308525070637244042934338228670691436072325551
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest/run.log
... and 8 more failures.
0.edn_genbits.26888793627473663153385518551493984488316040412206643614844705994708071256935
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_genbits/latest/run.log
1.edn_genbits.67538773077910515854492749456733454701786550429019763942351653980105998085317
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest/run.log
... and 298 more failures.
0.edn_stress_all.97379126157700357078568262922072117301214936228798329075445380562625150866400
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest/run.log
1.edn_stress_all.55311209816532170505845099608665325131873227450177039312150784390319877322594
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest/run.log
... and 48 more failures.
0.edn_stress_all_with_rand_reset.97417494709890291998158856408366454972912982227629473487579059605826293484756
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
1.edn_stress_all_with_rand_reset.4725656831817529299537647770003087792883839954401133655844628374836342251995
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.