EDN Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.110s	64.289us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.950s	17.082us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.970s	57.845us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.600s	544.709us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.260s	194.368us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.760s	111.330us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.970s	57.845us	20	20	100.00
		edn_csr_aliasing	1.260s	194.368us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	8.620s	1.129ms	300	300	100.00
V2	csrng_commands	edn_genbits	8.620s	1.129ms	300	300	100.00
V2	genbits	edn_genbits	8.620s	1.129ms	300	300	100.00
V2	interrupts	edn_intr	1.550s	53.431us	50	50	100.00
V2	alerts	edn_alert	1.260s	261.699us	50	50	100.00
V2	errs	edn_err	1.660s	33.560us	90	100	90.00
V2	disable	edn_disable	1.160s	27.898us	50	50	100.00
		edn_disable_auto_req_mode	1.610s	32.880us	48	50	96.00
V2	stress_all	edn_stress_all	5.350s	2.029ms	50	50	100.00
V2	intr_test	edn_intr_test	0.980s	27.159us	50	50	100.00
V2	alert_test	edn_alert_test	1.380s	42.608us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.370s	239.545us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.370s	239.545us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.950s	17.082us	5	5	100.00
		edn_csr_rw	0.970s	57.845us	20	20	100.00
		edn_csr_aliasing	1.260s	194.368us	5	5	100.00
		edn_same_csr_outstanding	1.280s	86.521us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.950s	17.082us	5	5	100.00
		edn_csr_rw	0.970s	57.845us	20	20	100.00
		edn_csr_aliasing	1.260s	194.368us	5	5	100.00
		edn_same_csr_outstanding	1.280s	86.521us	20	20	100.00
V2		TOTAL			778	790	98.48
V2S	tl_intg_err	edn_sec_cm	8.770s	536.467us	5	5	100.00
		edn_tl_intg_err	3.710s	161.241us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.050s	15.358us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.260s	261.699us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.770s	536.467us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.770s	536.467us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.770s	536.467us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.260s	261.699us	50	50	100.00
		edn_sec_cm	8.770s	536.467us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.260s	261.699us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.710s	161.241us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.160m	112.644ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.65	98.70	91.81	96.79	89.24	97.62	96.60	98.78

Failure Buckets

Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 10 failures:

Test edn_err has 10 failures.

7.edn_err.15478733351647791275464563754013770570306574182155460658273728652480298653503
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2342891 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

27.edn_err.12751598283733195968739763091395703329182816909483931447631849204701937280070
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/27.edn_err/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 24
  csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 8962445 ps, Illegal state
    bin il of coverpoint csrng_cmd_cp in covergroup

... and 8 more failures.

UVM_ERROR (edn_scoreboard.sv:270) [scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (* [*] vs * [*]) has 2 failures:
- Test edn_disable_auto_req_mode has 2 failures.
  - 3.edn_disable_auto_req_mode.90459470953435700326811660991415072865498949960022854724673783664872169719862
    Line 260, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/3.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  25300364 ps: (edn_scoreboard.sv:270) [uvm_test_top.env.scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (1 [0x1] vs 0 [0x0])
  UVM_INFO @  25300364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.edn_disable_auto_req_mode.30022859809722259553887059192007151296317265990353208003070306451189919954839
    Line 260, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @ 113067860 ps: (edn_scoreboard.sv:270) [uvm_test_top.env.scoreboard] Check failed sw_cmd_ack == item.d_data[cmd_ack] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 113067860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```