EDN Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.610us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	16.756us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	15.159us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.910s	518.216us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.480s	67.093us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.700s	46.917us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	15.159us	20	20	100.00
		edn_csr_aliasing	1.480s	67.093us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.850s	464.400us	300	300	100.00
V2	csrng_commands	edn_genbits	3.850s	464.400us	300	300	100.00
V2	genbits	edn_genbits	3.850s	464.400us	300	300	100.00
V2	interrupts	edn_intr	1.200s	22.335us	50	50	100.00
V2	alerts	edn_alert	1.110s	23.087us	50	50	100.00
V2	errs	edn_err	1.360s	27.027us	96	100	96.00
V2	disable	edn_disable	0.930s	22.129us	50	50	100.00
		edn_disable_auto_req_mode	1.530s	35.867us	38	50	76.00
V2	stress_all	edn_stress_all	7.340s	388.416us	50	50	100.00
V2	intr_test	edn_intr_test	1.000s	52.235us	50	50	100.00
V2	alert_test	edn_alert_test	1.450s	50.716us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.980s	876.471us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.980s	876.471us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	16.756us	5	5	100.00
		edn_csr_rw	0.990s	15.159us	20	20	100.00
		edn_csr_aliasing	1.480s	67.093us	5	5	100.00
		edn_same_csr_outstanding	1.460s	100.326us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	16.756us	5	5	100.00
		edn_csr_rw	0.990s	15.159us	20	20	100.00
		edn_csr_aliasing	1.480s	67.093us	5	5	100.00
		edn_same_csr_outstanding	1.460s	100.326us	20	20	100.00
V2		TOTAL			774	790	97.97
V2S	tl_intg_err	edn_sec_cm	8.020s	540.004us	5	5	100.00
		edn_tl_intg_err	3.510s	160.254us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.980s	16.975us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.110s	23.087us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.020s	540.004us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.020s	540.004us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.020s	540.004us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.110s	23.087us	50	50	100.00
		edn_sec_cm	8.020s	540.004us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.110s	23.087us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.510s	160.254us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	49.090m	124.558ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			964	980	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.19	98.73	93.82	90.97	89.47	98.16	96.56	98.58

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:305) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 11 failures:
- Test edn_disable_auto_req_mode has 11 failures.
  - 0.edn_disable_auto_req_mode.89045385495080448837699462895051538350812873967124240064417301095228641465808
    Line 260, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  53449825 ps: (edn_scoreboard.sv:305) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  53449825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.edn_disable_auto_req_mode.80079398189147520421557559866881983132752547027860248823009810158247369333554
    Line 257, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  85574939 ps: (edn_scoreboard.sv:305) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  85574939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

Offending 'valid' has 4 failures:

Test edn_err has 4 failures.

16.edn_err.42051347525811602418970462133099401439672987140346610395691245473404045269571
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/16.edn_err/latest/run.log

      Offending 'valid'
  UVM_ERROR @  12787707 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @  12787707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.edn_err.104985716657652729026427274495858953453558980610476588026726401595905006759732
Line 303, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/40.edn_err/latest/run.log

      Offending 'valid'
  UVM_ERROR @   8830761 ps: (push_pull_if.sv:124) [ASSERT FAILED] ValidHighUntilReady_A
  UVM_INFO @   8830761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 34.edn_disable_auto_req_mode.54438449877028346308541447823089340069408016445079604412853659276518570724924
    Line 262, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/34.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```