93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 20 | 0.00 | ||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | firmware | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | csrng_commands | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | genbits | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | interrupts | edn_intr | 0 | 50 | 0.00 | ||
| V2 | alerts | edn_alert | 0 | 50 | 0.00 | ||
| V2 | errs | edn_err | 0 | 100 | 0.00 | ||
| V2 | disable | edn_disable | 0 | 50 | 0.00 | ||
| edn_disable_auto_req_mode | 0 | 50 | 0.00 | ||||
| V2 | stress_all | edn_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | edn_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 790 | 0.00 | |||
| V2S | tl_intg_err | edn_sec_cm | 0 | 5 | 0.00 | ||
| edn_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 0 | 10 | 0.00 | ||
| V2S | sec_cm_config_mubi | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0 | 50 | 0.00 | ||
| edn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 35 | 0.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 980 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 982 failures:
0.edn_smoke.96205515319046313962741902669163102446428255850086903361477481300494731037745
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_smoke/latest/run.log
1.edn_smoke.61407122031163445799293513369790490304535898677218997311505832874944243587592
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_smoke/latest/run.log
... and 48 more failures.
0.edn_regwen.45328476236094671791374614684603016096652635925018495764500925954536709136025
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_regwen/latest/run.log
1.edn_regwen.85929015402498840299573341776444848102569396096596382707778937714463970654975
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest/run.log
... and 8 more failures.
0.edn_genbits.9110101539363770342810103673425962137300376523882028130444954614914226138010
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_genbits/latest/run.log
1.edn_genbits.85159768648677029762335965494066874643877083047858367566308538553695008717263
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest/run.log
... and 298 more failures.
0.edn_stress_all.90154054684603091681982852060961230889404867954830359644482641440661973131952
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest/run.log
1.edn_stress_all.17625243922852352424403057000109254390521713116376313199687343741667413392362
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest/run.log
... and 48 more failures.
0.edn_stress_all_with_rand_reset.88918740256748536447632540499447082070413355352195299755847171851436878649977
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
1.edn_stress_all_with_rand_reset.79161318099259799755611848651407529129563167358389869159292358481408554129728
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Job edn-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/default/build.log
Job ID: smart:97bd598a-8f3d-47c4-8fe4-9024b98f5b2e
Job edn-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/cover_reg_top/build.log
Job ID: smart:b3620dd9-17eb-496a-9b5f-a00840ae1c41