EDN Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.100s	18.015us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	66.256us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.980s	21.986us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.170s	262.131us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.620s	410.703us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	4.560s	922.348us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.980s	21.986us	20	20	100.00
		edn_csr_aliasing	1.620s	410.703us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.400s	399.480us	300	300	100.00
V2	csrng_commands	edn_genbits	4.400s	399.480us	300	300	100.00
V2	genbits	edn_genbits	4.400s	399.480us	300	300	100.00
V2	interrupts	edn_intr	1.250s	21.729us	50	50	100.00
V2	alerts	edn_alert	1.680s	335.789us	50	50	100.00
V2	errs	edn_err	1.480s	34.721us	100	100	100.00
V2	disable	edn_disable	0.970s	20.457us	50	50	100.00
		edn_disable_auto_req_mode	1.400s	42.324us	38	50	76.00
V2	stress_all	edn_stress_all	5.960s	293.114us	50	50	100.00
V2	intr_test	edn_intr_test	0.930s	15.195us	50	50	100.00
V2	alert_test	edn_alert_test	1.060s	43.881us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.950s	503.446us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.950s	503.446us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	66.256us	5	5	100.00
		edn_csr_rw	0.980s	21.986us	20	20	100.00
		edn_csr_aliasing	1.620s	410.703us	5	5	100.00
		edn_same_csr_outstanding	1.480s	40.697us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	66.256us	5	5	100.00
		edn_csr_rw	0.980s	21.986us	20	20	100.00
		edn_csr_aliasing	1.620s	410.703us	5	5	100.00
		edn_same_csr_outstanding	1.480s	40.697us	20	20	100.00
V2		TOTAL			778	790	98.48
V2S	tl_intg_err	edn_sec_cm	8.380s	532.856us	5	5	100.00
		edn_tl_intg_err	2.410s	110.417us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	19.230us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.680s	335.789us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.380s	532.856us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.380s	532.856us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.380s	532.856us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.680s	335.789us	50	50	100.00
		edn_sec_cm	8.380s	532.856us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.680s	335.789us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.410s	110.417us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	57.530m	284.742ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.80	98.27	93.63	96.79	81.50	96.87	96.58	92.95

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 12 failures:
  • Test edn_disable_auto_req_mode has 12 failures.

    • 0.edn_disable_auto_req_mode.73767922202393992135798384372665845328028209180451691351019056944539783885116
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @ 124897165 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 11 [0xb]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @ 124897165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.edn_disable_auto_req_mode.82191794435811334111576630182707877874742493351200269660057716436656047703283
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  64363571 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  64363571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

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