EDN Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: df66f8a42e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	17.380us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	15.594us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.920s	172.050us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.410s	315.316us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.230s	33.366us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.960s	111.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	172.050us	20	20	100.00
		edn_csr_aliasing	1.230s	33.366us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.546m	4.567ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.546m	4.567ms	300	300	100.00
V2	genbits	edn_genbits	1.546m	4.567ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	22.520us	50	50	100.00
V2	alerts	edn_alert	1.560s	428.663us	50	50	100.00
V2	errs	edn_err	1.400s	29.115us	100	100	100.00
V2	disable	edn_disable	1.210s	13.986us	50	50	100.00
		edn_disable_auto_req_mode	1.380s	49.798us	42	50	84.00
V2	stress_all	edn_stress_all	6.350s	323.302us	50	50	100.00
V2	intr_test	edn_intr_test	1.040s	36.987us	50	50	100.00
V2	alert_test	edn_alert_test	1.170s	71.295us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.070s	102.365us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.070s	102.365us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	15.594us	5	5	100.00
		edn_csr_rw	0.920s	172.050us	20	20	100.00
		edn_csr_aliasing	1.230s	33.366us	5	5	100.00
		edn_same_csr_outstanding	1.590s	676.156us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	15.594us	5	5	100.00
		edn_csr_rw	0.920s	172.050us	20	20	100.00
		edn_csr_aliasing	1.230s	33.366us	5	5	100.00
		edn_same_csr_outstanding	1.590s	676.156us	20	20	100.00
V2		TOTAL			782	790	98.99
V2S	tl_intg_err	edn_sec_cm	6.490s	1.230ms	5	5	100.00
		edn_tl_intg_err	3.120s	175.748us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.980s	17.932us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.560s	428.663us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.490s	1.230ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.490s	1.230ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.490s	1.230ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.560s	428.663us	50	50	100.00
		edn_sec_cm	6.490s	1.230ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.560s	428.663us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.120s	175.748us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.405h	1.156s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			972	980	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.58	98.27	93.56	96.84	79.77	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 8 failures:
  • Test edn_disable_auto_req_mode has 8 failures.

    • 6.edn_disable_auto_req_mode.68958055730887427837051881773415362143328686896297527806254431430894609279930
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  62422609 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  62422609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.edn_disable_auto_req_mode.111041034649304708588564068396656511847537250602166179320089908604561329272923
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  60896190 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  60896190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

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