EDN Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.040s	16.555us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.100s	247.043us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	13.949us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.310s	224.682us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.350s	28.200us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.560s	23.970us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	13.949us	20	20	100.00
		edn_csr_aliasing	1.350s	28.200us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.080s	958.301us	300	300	100.00
V2	csrng_commands	edn_genbits	6.080s	958.301us	300	300	100.00
V2	genbits	edn_genbits	6.080s	958.301us	300	300	100.00
V2	interrupts	edn_intr	1.220s	20.968us	50	50	100.00
V2	alerts	edn_alert	1.400s	100.637us	50	50	100.00
V2	errs	edn_err	1.590s	37.775us	100	100	100.00
V2	disable	edn_disable	1.000s	14.688us	50	50	100.00
		edn_disable_auto_req_mode	1.400s	41.541us	37	50	74.00
V2	stress_all	edn_stress_all	7.700s	384.647us	50	50	100.00
V2	intr_test	edn_intr_test	1.010s	25.742us	50	50	100.00
V2	alert_test	edn_alert_test	1.540s	57.940us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.000s	810.129us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.000s	810.129us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.100s	247.043us	5	5	100.00
		edn_csr_rw	1.010s	13.949us	20	20	100.00
		edn_csr_aliasing	1.350s	28.200us	5	5	100.00
		edn_same_csr_outstanding	1.540s	236.309us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.100s	247.043us	5	5	100.00
		edn_csr_rw	1.010s	13.949us	20	20	100.00
		edn_csr_aliasing	1.350s	28.200us	5	5	100.00
		edn_same_csr_outstanding	1.540s	236.309us	20	20	100.00
V2		TOTAL			777	790	98.35
V2S	tl_intg_err	edn_sec_cm	5.900s	731.237us	5	5	100.00
		edn_tl_intg_err	2.950s	1.259ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.060s	18.244us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.400s	100.637us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.900s	731.237us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.900s	731.237us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.900s	731.237us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.400s	100.637us	50	50	100.00
		edn_sec_cm	5.900s	731.237us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.400s	100.637us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.950s	1.259ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	37.324m	232.065ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			967	980	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.96	98.27	93.44	96.79	82.66	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 13 failures:
  • Test edn_disable_auto_req_mode has 13 failures.

    • 8.edn_disable_auto_req_mode.92959455233343402668005060835241595975964907639911597877937637703138092731962
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  75493403 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  75493403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.edn_disable_auto_req_mode.115280010565357061385803231346290539642983591301507141109469192651646865486640
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  49620128 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  49620128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

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