EDN Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	17.954us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	190.573us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.020s	17.204us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.560s	923.172us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.260s	20.540us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.770s	52.251us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.020s	17.204us	20	20	100.00
		edn_csr_aliasing	1.260s	20.540us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.416m	10.043ms	299	300	99.67
V2	csrng_commands	edn_genbits	1.416m	10.043ms	299	300	99.67
V2	genbits	edn_genbits	1.416m	10.043ms	299	300	99.67
V2	interrupts	edn_intr	1.260s	21.154us	50	50	100.00
V2	alerts	edn_alert	1.420s	221.447us	50	50	100.00
V2	errs	edn_err	1.510s	36.107us	100	100	100.00
V2	disable	edn_disable	0.980s	13.311us	50	50	100.00
		edn_disable_auto_req_mode	1.510s	51.649us	41	50	82.00
V2	stress_all	edn_stress_all	7.750s	393.264us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	43.931us	50	50	100.00
V2	alert_test	edn_alert_test	1.270s	30.221us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.410s	119.932us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.410s	119.932us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	190.573us	5	5	100.00
		edn_csr_rw	1.020s	17.204us	20	20	100.00
		edn_csr_aliasing	1.260s	20.540us	5	5	100.00
		edn_same_csr_outstanding	1.400s	37.421us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	190.573us	5	5	100.00
		edn_csr_rw	1.020s	17.204us	20	20	100.00
		edn_csr_aliasing	1.260s	20.540us	5	5	100.00
		edn_same_csr_outstanding	1.400s	37.421us	20	20	100.00
V2		TOTAL			780	790	98.73
V2S	tl_intg_err	edn_sec_cm	4.940s	305.581us	5	5	100.00
		edn_tl_intg_err	3.120s	151.200us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.990s	18.733us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.420s	221.447us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.940s	305.581us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.940s	305.581us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.940s	305.581us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.420s	221.447us	50	50	100.00
		edn_sec_cm	4.940s	305.581us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.420s	221.447us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.120s	151.200us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.333m	281.426ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			970	980	98.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.85	98.27	93.56	96.84	81.50	96.87	96.58	93.35

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 9 failures:
  • Test edn_disable_auto_req_mode has 9 failures.

    • 3.edn_disable_auto_req_mode.112413068472639247329446032476712245093898890515078019707114334315019405001838
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/3.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @ 143827507 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @ 143827507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.edn_disable_auto_req_mode.80630958025932053808977174526825446652601433893996316009751908114076214671826
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  24658484 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  24658484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=*) == * has 1 failures:
  • Test edn_genbits has 1 failures.

    • 63.edn_genbits.109129228147595211021715960643404475548898462954293415831419835830002103817380
      Line 256, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/63.edn_genbits/latest/run.log

        UVM_FATAL @ 10043246926 ps: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout edn_reg_block.main_sm_state (addr=0x9137bec4) == 0xbf
        UVM_INFO @ 10043246926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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