EDN Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.080s	23.385us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	17.857us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.930s	13.437us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.110s	344.505us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.500s	141.610us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.210s	139.549us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.930s	13.437us	20	20	100.00
		edn_csr_aliasing	1.500s	141.610us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.110s	579.590us	300	300	100.00
V2	csrng_commands	edn_genbits	6.110s	579.590us	300	300	100.00
V2	genbits	edn_genbits	6.110s	579.590us	300	300	100.00
V2	interrupts	edn_intr	1.230s	22.331us	50	50	100.00
V2	alerts	edn_alert	1.370s	86.020us	50	50	100.00
V2	errs	edn_err	1.400s	29.453us	100	100	100.00
V2	disable	edn_disable	0.950s	13.992us	50	50	100.00
		edn_disable_auto_req_mode	1.320s	46.971us	38	50	76.00
V2	stress_all	edn_stress_all	6.860s	365.960us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	27.289us	50	50	100.00
V2	alert_test	edn_alert_test	1.100s	30.506us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.600s	125.191us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.600s	125.191us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	17.857us	5	5	100.00
		edn_csr_rw	0.930s	13.437us	20	20	100.00
		edn_csr_aliasing	1.500s	141.610us	5	5	100.00
		edn_same_csr_outstanding	1.460s	37.095us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	17.857us	5	5	100.00
		edn_csr_rw	0.930s	13.437us	20	20	100.00
		edn_csr_aliasing	1.500s	141.610us	5	5	100.00
		edn_same_csr_outstanding	1.460s	37.095us	20	20	100.00
V2		TOTAL			778	790	98.48
V2S	tl_intg_err	edn_sec_cm	7.010s	2.104ms	5	5	100.00
		edn_tl_intg_err	4.030s	197.450us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.040s	18.158us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.370s	86.020us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.010s	2.104ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.010s	2.104ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.010s	2.104ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.370s	86.020us	50	50	100.00
		edn_sec_cm	7.010s	2.104ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.370s	86.020us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.030s	197.450us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.171h	1.184s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.63	98.27	93.44	96.79	80.35	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 11 failures:
  • Test edn_disable_auto_req_mode has 11 failures.

    • 3.edn_disable_auto_req_mode.20737077454706320312217187472645251424787232453807998164205224588196883989951
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/3.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  30285241 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  30285241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.edn_disable_auto_req_mode.45958999735884581282065555960423162642968829592443707261219745974780637384374
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @ 153548377 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @ 153548377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
  • Test edn_disable_auto_req_mode has 1 failures.

    • 21.edn_disable_auto_req_mode.68859434788939345828378348838628173180298318014452802228349609120854941878294
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/21.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  13580141 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  13580141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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