EDN Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	19.320us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.060s	17.427us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	17.746us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.220s	1.014ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.630s	568.605us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.720s	66.839us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	17.746us	20	20	100.00
		edn_csr_aliasing	1.630s	568.605us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	2.446m	10.971ms	300	300	100.00
V2	csrng_commands	edn_genbits	2.446m	10.971ms	300	300	100.00
V2	genbits	edn_genbits	2.446m	10.971ms	300	300	100.00
V2	interrupts	edn_intr	1.270s	21.781us	50	50	100.00
V2	alerts	edn_alert	1.380s	219.602us	50	50	100.00
V2	errs	edn_err	1.410s	56.239us	100	100	100.00
V2	disable	edn_disable	0.970s	14.112us	50	50	100.00
		edn_disable_auto_req_mode	1.450s	76.217us	36	50	72.00
V2	stress_all	edn_stress_all	7.240s	729.498us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	22.780us	50	50	100.00
V2	alert_test	edn_alert_test	1.210s	36.667us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.530s	120.432us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.530s	120.432us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.060s	17.427us	5	5	100.00
		edn_csr_rw	0.960s	17.746us	20	20	100.00
		edn_csr_aliasing	1.630s	568.605us	5	5	100.00
		edn_same_csr_outstanding	1.580s	116.512us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.060s	17.427us	5	5	100.00
		edn_csr_rw	0.960s	17.746us	20	20	100.00
		edn_csr_aliasing	1.630s	568.605us	5	5	100.00
		edn_same_csr_outstanding	1.580s	116.512us	20	20	100.00
V2		TOTAL			776	790	98.23
V2S	tl_intg_err	edn_sec_cm	9.710s	1.274ms	5	5	100.00
		edn_tl_intg_err	3.050s	145.153us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.030s	17.959us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	219.602us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.710s	1.274ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.710s	1.274ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.710s	1.274ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	219.602us	50	50	100.00
		edn_sec_cm	9.710s	1.274ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	219.602us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.050s	145.153us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.143m	713.612ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			966	980	98.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.94	98.27	93.63	96.79	82.08	96.87	96.58	93.35

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 13 failures:
  • Test edn_disable_auto_req_mode has 13 failures.

    • 5.edn_disable_auto_req_mode.6156874660856662762173228562809841043348105938197437137299146568557231942298
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  52657363 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  52657363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.edn_disable_auto_req_mode.75382810687269711741489512984872668881932112706546246786828876519102511134944
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  36704495 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  36704495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable_auto_req_mode has 1 failures.

    • 45.edn_disable_auto_req_mode.51383207041050485400466169107155679060217655905310780783430915717304180428118
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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