c30684b3ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 1.050s | 19.929us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.950s | 17.843us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 0.970s | 17.291us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.470s | 264.297us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.550s | 419.052us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 1.920s | 99.515us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.970s | 17.291us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.550s | 419.052us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | firmware | edn_genbits | 1.155m | 2.216ms | 300 | 300 | 100.00 |
| V2 | csrng_commands | edn_genbits | 1.155m | 2.216ms | 300 | 300 | 100.00 |
| V2 | genbits | edn_genbits | 1.155m | 2.216ms | 300 | 300 | 100.00 |
| V2 | interrupts | edn_intr | 1.210s | 23.329us | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 1.470s | 241.687us | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 1.350s | 42.638us | 100 | 100 | 100.00 |
| V2 | disable | edn_disable | 0.950s | 12.020us | 50 | 50 | 100.00 |
| edn_disable_auto_req_mode | 1.450s | 45.377us | 41 | 50 | 82.00 | ||
| V2 | stress_all | edn_stress_all | 7.770s | 376.215us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 0.960s | 18.575us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 1.460s | 50.399us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 4.200s | 127.892us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 4.200s | 127.892us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.950s | 17.843us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.970s | 17.291us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.550s | 419.052us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.530s | 148.034us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.950s | 17.843us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.970s | 17.291us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.550s | 419.052us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.530s | 148.034us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 781 | 790 | 98.86 | |||
| V2S | tl_intg_err | edn_sec_cm | 6.600s | 731.449us | 5 | 5 | 100.00 |
| edn_tl_intg_err | 2.930s | 117.365us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.090s | 34.665us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.470s | 241.687us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 6.600s | 731.449us | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 6.600s | 731.449us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 6.600s | 731.449us | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.470s | 241.687us | 50 | 50 | 100.00 |
| edn_sec_cm | 6.600s | 731.449us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.470s | 241.687us | 50 | 50 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 2.930s | 117.365us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 42.761m | 222.252ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 970 | 980 | 98.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 11 | 11 | 10 | 90.91 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.94 | 98.27 | 93.63 | 96.79 | 82.08 | 96.87 | 96.58 | 93.35 |
UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 9 failures:
11.edn_disable_auto_req_mode.23453637025949746327700709652461569869710243409731286468935500218918589829290
Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 40642598 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 40642598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.edn_disable_auto_req_mode.2584699670396118926894122065813622157386989552542159717272132521343959304605
Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 29643140 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 29643140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
40.edn_stress_all_with_rand_reset.4770632698208988464801626123259117217752114307088450616701587475555278018352
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:20bb72c3-d019-4e68-89e8-fec912f6e7e6