EDN Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.100s	26.497us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	27.530us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	15.549us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.480s	224.000us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.550s	34.951us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.130s	97.723us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	15.549us	20	20	100.00
		edn_csr_aliasing	1.550s	34.951us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	6.460s	963.801us	300	300	100.00
V2	csrng_commands	edn_genbits	6.460s	963.801us	300	300	100.00
V2	genbits	edn_genbits	6.460s	963.801us	300	300	100.00
V2	interrupts	edn_intr	1.230s	20.839us	50	50	100.00
V2	alerts	edn_alert	1.480s	301.557us	50	50	100.00
V2	errs	edn_err	1.540s	42.191us	100	100	100.00
V2	disable	edn_disable	0.970s	20.860us	50	50	100.00
		edn_disable_auto_req_mode	1.490s	140.379us	37	50	74.00
V2	stress_all	edn_stress_all	7.000s	365.498us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	15.584us	50	50	100.00
V2	alert_test	edn_alert_test	1.070s	55.576us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.490s	2.053ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.490s	2.053ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	27.530us	5	5	100.00
		edn_csr_rw	1.000s	15.549us	20	20	100.00
		edn_csr_aliasing	1.550s	34.951us	5	5	100.00
		edn_same_csr_outstanding	1.540s	195.119us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	27.530us	5	5	100.00
		edn_csr_rw	1.000s	15.549us	20	20	100.00
		edn_csr_aliasing	1.550s	34.951us	5	5	100.00
		edn_same_csr_outstanding	1.540s	195.119us	20	20	100.00
V2		TOTAL			777	790	98.35
V2S	tl_intg_err	edn_sec_cm	6.970s	3.212ms	5	5	100.00
		edn_tl_intg_err	9.550s	641.138us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.080s	16.491us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.480s	301.557us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.970s	3.212ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.970s	3.212ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.970s	3.212ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.480s	301.557us	50	50	100.00
		edn_sec_cm	6.970s	3.212ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.480s	301.557us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	9.550s	641.138us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	40.995m	410.670ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			967	980	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.00	98.27	93.63	96.84	82.66	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 13 failures:
  • Test edn_disable_auto_req_mode has 13 failures.

    • 0.edn_disable_auto_req_mode.55089652693118102885977531883741991081689045610499217559865349954231692884148
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  48763931 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  48763931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.edn_disable_auto_req_mode.93051571593478222707039567386134900057318654079180301530163961843747383830105
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  54024138 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 11 [0xb]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  54024138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

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