8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 1.060s | 14.979us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.960s | 56.137us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 0.970s | 32.001us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.010s | 253.862us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.650s | 53.812us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 2.120s | 34.628us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.970s | 32.001us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.650s | 53.812us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | firmware | edn_genbits | 4.180s | 291.929us | 300 | 300 | 100.00 |
| V2 | csrng_commands | edn_genbits | 4.180s | 291.929us | 300 | 300 | 100.00 |
| V2 | genbits | edn_genbits | 4.180s | 291.929us | 300 | 300 | 100.00 |
| V2 | interrupts | edn_intr | 1.180s | 23.023us | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 1.610s | 377.837us | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 1.380s | 28.515us | 100 | 100 | 100.00 |
| V2 | disable | edn_disable | 0.940s | 11.707us | 50 | 50 | 100.00 |
| edn_disable_auto_req_mode | 1.600s | 45.773us | 42 | 50 | 84.00 | ||
| V2 | stress_all | edn_stress_all | 6.810s | 373.036us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 0.990s | 74.724us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 2.250s | 117.825us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 4.780s | 1.891ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 4.780s | 1.891ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.960s | 56.137us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.970s | 32.001us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.650s | 53.812us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.480s | 41.837us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.960s | 56.137us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.970s | 32.001us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.650s | 53.812us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.480s | 41.837us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 782 | 790 | 98.99 | |||
| V2S | tl_intg_err | edn_sec_cm | 6.670s | 464.029us | 5 | 5 | 100.00 |
| edn_tl_intg_err | 3.000s | 138.625us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.050s | 19.841us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.610s | 377.837us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 6.670s | 464.029us | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 6.670s | 464.029us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 6.670s | 464.029us | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.610s | 377.837us | 50 | 50 | 100.00 |
| edn_sec_cm | 6.670s | 464.029us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.610s | 377.837us | 50 | 50 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 3.000s | 138.625us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 52.245m | 270.278ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 971 | 980 | 99.08 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 11 | 11 | 10 | 90.91 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.99 | 98.27 | 93.63 | 96.79 | 82.66 | 96.87 | 96.58 | 93.15 |
UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 8 failures:
2.edn_disable_auto_req_mode.104646472509141944246636403965818869550280024691250785830604630619828191290664
Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 25681683 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 25681683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.edn_disable_auto_req_mode.67418730981697039111820397151889546956582838884256459721074155943786894227120
Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/4.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 39207134 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 8 [0x8]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 39207134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
47.edn_stress_all_with_rand_reset.7823790397627895928505424385253785197212625113537857965322790123033818722250
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/47.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:6b8e9d3c-f9b0-498e-a06c-76a4dde9a150