EDN Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.020s 14.594us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.910s 49.732us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 16.690us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.390s 524.104us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.480s 37.599us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.950s 98.935us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 16.690us 20 20 100.00
edn_csr_aliasing 1.480s 37.599us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.544m 4.569ms 300 300 100.00
V2 csrng_commands edn_genbits 1.544m 4.569ms 300 300 100.00
V2 genbits edn_genbits 1.544m 4.569ms 300 300 100.00
V2 interrupts edn_intr 1.220s 25.886us 50 50 100.00
V2 alerts edn_alert 1.410s 154.799us 50 50 100.00
V2 errs edn_err 1.330s 28.389us 100 100 100.00
V2 disable edn_disable 0.960s 25.197us 50 50 100.00
edn_disable_auto_req_mode 1.410s 41.460us 39 50 78.00
V2 stress_all edn_stress_all 7.090s 369.116us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 17.620us 50 50 100.00
V2 alert_test edn_alert_test 1.100s 25.244us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.090s 704.591us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.090s 704.591us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.910s 49.732us 5 5 100.00
edn_csr_rw 0.990s 16.690us 20 20 100.00
edn_csr_aliasing 1.480s 37.599us 5 5 100.00
edn_same_csr_outstanding 1.430s 34.871us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.910s 49.732us 5 5 100.00
edn_csr_rw 0.990s 16.690us 20 20 100.00
edn_csr_aliasing 1.480s 37.599us 5 5 100.00
edn_same_csr_outstanding 1.430s 34.871us 20 20 100.00
V2 TOTAL 779 790 98.61
V2S tl_intg_err edn_sec_cm 6.190s 1.538ms 5 5 100.00
edn_tl_intg_err 2.730s 112.120us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 22.260us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 154.799us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.190s 1.538ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.190s 1.538ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.190s 1.538ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 154.799us 50 50 100.00
edn_sec_cm 6.190s 1.538ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 154.799us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.730s 112.120us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 38.960m 1.081s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 969 980 98.88

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.93 98.27 93.56 96.79 82.08 96.87 96.58 93.35

Failure Buckets

Past Results