EDN Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.030s	18.250us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.960s	53.705us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.910s	14.864us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.040s	202.501us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	61.135us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.110s	194.684us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.910s	14.864us	20	20	100.00
		edn_csr_aliasing	1.420s	61.135us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.210m	2.319ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.210m	2.319ms	300	300	100.00
V2	genbits	edn_genbits	1.210m	2.319ms	300	300	100.00
V2	interrupts	edn_intr	1.280s	21.197us	50	50	100.00
V2	alerts	edn_alert	1.380s	264.132us	50	50	100.00
V2	errs	edn_err	1.510s	49.726us	100	100	100.00
V2	disable	edn_disable	1.000s	14.034us	50	50	100.00
		edn_disable_auto_req_mode	1.540s	54.190us	39	50	78.00
V2	stress_all	edn_stress_all	6.530s	442.042us	50	50	100.00
V2	intr_test	edn_intr_test	0.920s	17.696us	50	50	100.00
V2	alert_test	edn_alert_test	1.200s	29.620us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.120s	260.380us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.120s	260.380us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.960s	53.705us	5	5	100.00
		edn_csr_rw	0.910s	14.864us	20	20	100.00
		edn_csr_aliasing	1.420s	61.135us	5	5	100.00
		edn_same_csr_outstanding	1.450s	72.604us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.960s	53.705us	5	5	100.00
		edn_csr_rw	0.910s	14.864us	20	20	100.00
		edn_csr_aliasing	1.420s	61.135us	5	5	100.00
		edn_same_csr_outstanding	1.450s	72.604us	20	20	100.00
V2		TOTAL			779	790	98.61
V2S	tl_intg_err	edn_sec_cm	1.214m	10.193ms	4	5	80.00
		edn_tl_intg_err	3.420s	309.338us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.090s	18.735us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	264.132us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	1.214m	10.193ms	4	5	80.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	1.214m	10.193ms	4	5	80.00
V2S	sec_cm_ctr_redun	edn_sec_cm	1.214m	10.193ms	4	5	80.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	264.132us	50	50	100.00
		edn_sec_cm	1.214m	10.193ms	4	5	80.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	264.132us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.420s	309.338us	20	20	100.00
V2S		TOTAL			34	35	97.14
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	57.453m	531.823ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.72	98.27	93.44	96.79	80.92	96.87	96.58	93.15

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 11 failures:
- Test edn_disable_auto_req_mode has 11 failures.
  - 4.edn_disable_auto_req_mode.51391916297725208065055089122122301636462627450636204323261927648976369918684
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/4.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  23101980 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  23101980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.edn_disable_auto_req_mode.62828325181978246951158562736759240253676212085491698490946696436720790855954
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/12.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  69483334 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 11 [0xb]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  69483334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (cip_base_vseq.sv:636) [edn_common_vseq] timeout wait for alert handshake:fatal_alert has 1 failures:
- Test edn_sec_cm has 1 failures.
  - 0.edn_sec_cm.97983760455212927214166890411899996342520334269089128286715421935393598621668
    Line 313, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log
```
  UVM_FATAL @ 10192874683 ps: (cip_base_vseq.sv:636) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] timeout wait for alert handshake:fatal_alert
  UVM_INFO @ 10192874683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e844018f2c`