EDN Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.060s 19.262us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.110s 27.143us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 18.463us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.270s 911.787us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.490s 39.999us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.600s 234.807us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 18.463us 20 20 100.00
edn_csr_aliasing 1.490s 39.999us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.261m 3.000ms 300 300 100.00
V2 csrng_commands edn_genbits 1.261m 3.000ms 300 300 100.00
V2 genbits edn_genbits 1.261m 3.000ms 300 300 100.00
V2 interrupts edn_intr 1.260s 22.203us 50 50 100.00
V2 alerts edn_alert 1.480s 312.763us 50 50 100.00
V2 errs edn_err 1.440s 32.764us 100 100 100.00
V2 disable edn_disable 0.910s 17.793us 50 50 100.00
edn_disable_auto_req_mode 1.380s 56.984us 34 50 68.00
V2 stress_all edn_stress_all 7.330s 399.632us 50 50 100.00
V2 intr_test edn_intr_test 1.060s 117.157us 50 50 100.00
V2 alert_test edn_alert_test 1.320s 64.749us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.850s 116.495us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.850s 116.495us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.110s 27.143us 5 5 100.00
edn_csr_rw 0.960s 18.463us 20 20 100.00
edn_csr_aliasing 1.490s 39.999us 5 5 100.00
edn_same_csr_outstanding 1.530s 38.838us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.110s 27.143us 5 5 100.00
edn_csr_rw 0.960s 18.463us 20 20 100.00
edn_csr_aliasing 1.490s 39.999us 5 5 100.00
edn_same_csr_outstanding 1.530s 38.838us 20 20 100.00
V2 TOTAL 774 790 97.97
V2S tl_intg_err edn_sec_cm 7.630s 486.972us 5 5 100.00
edn_tl_intg_err 2.960s 147.919us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.960s 19.177us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.480s 312.763us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.630s 486.972us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.630s 486.972us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.630s 486.972us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.480s 312.763us 50 50 100.00
edn_sec_cm 7.630s 486.972us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.480s 312.763us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.960s 147.919us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 45.081m 210.805ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 964 980 98.37

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.91 98.27 93.63 96.79 82.08 96.87 96.58 93.15

Failure Buckets

Past Results