EDN Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	17.774us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	49.930us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.040s	24.457us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.300s	228.915us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.520s	131.232us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.480s	500.308us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.040s	24.457us	20	20	100.00
		edn_csr_aliasing	1.520s	131.232us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.513m	4.845ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.513m	4.845ms	300	300	100.00
V2	genbits	edn_genbits	1.513m	4.845ms	300	300	100.00
V2	interrupts	edn_intr	1.300s	26.417us	50	50	100.00
V2	alerts	edn_alert	1.370s	101.405us	50	50	100.00
V2	errs	edn_err	1.310s	25.397us	100	100	100.00
V2	disable	edn_disable	0.950s	14.711us	50	50	100.00
		edn_disable_auto_req_mode	1.360s	37.838us	45	50	90.00
V2	stress_all	edn_stress_all	5.290s	868.147us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	18.552us	50	50	100.00
V2	alert_test	edn_alert_test	3.740s	222.265us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.560s	276.046us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.560s	276.046us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	49.930us	5	5	100.00
		edn_csr_rw	1.040s	24.457us	20	20	100.00
		edn_csr_aliasing	1.520s	131.232us	5	5	100.00
		edn_same_csr_outstanding	1.470s	41.985us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	49.930us	5	5	100.00
		edn_csr_rw	1.040s	24.457us	20	20	100.00
		edn_csr_aliasing	1.520s	131.232us	5	5	100.00
		edn_same_csr_outstanding	1.470s	41.985us	20	20	100.00
V2		TOTAL			785	790	99.37
V2S	tl_intg_err	edn_sec_cm	6.370s	758.894us	5	5	100.00
		edn_tl_intg_err	4.320s	218.204us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	14.841us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.370s	101.405us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.370s	758.894us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.370s	758.894us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.370s	758.894us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.370s	101.405us	50	50	100.00
		edn_sec_cm	6.370s	758.894us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.370s	101.405us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.320s	218.204us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	51.282m	140.131ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			974	980	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.21	98.27	93.63	96.79	84.39	96.87	96.58	92.95

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 5 failures:
  • Test edn_disable_auto_req_mode has 5 failures.

    • 2.edn_disable_auto_req_mode.6584210694685689348542279457708754458138695309727103757433941838868835687096
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  23966537 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  23966537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.edn_disable_auto_req_mode.18446758140938905303771439372199157729926984865193729138365776718389111463197
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  13558936 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  13558936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 48.edn_stress_all_with_rand_reset.104435590303271887419802378630301093337554447601793956939262785135009959191331
      Line 319, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/48.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 773432341 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 773432341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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