EDN Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.110s 19.918us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.950s 19.790us 5 5 100.00
V1 csr_rw edn_csr_rw 1.000s 15.982us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.690s 677.087us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.440s 46.231us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.750s 26.176us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.000s 15.982us 20 20 100.00
edn_csr_aliasing 1.440s 46.231us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.680s 584.898us 300 300 100.00
V2 csrng_commands edn_genbits 4.680s 584.898us 300 300 100.00
V2 genbits edn_genbits 4.680s 584.898us 300 300 100.00
V2 interrupts edn_intr 1.270s 29.962us 50 50 100.00
V2 alerts edn_alert 1.700s 421.997us 50 50 100.00
V2 errs edn_err 1.550s 35.255us 100 100 100.00
V2 disable edn_disable 0.970s 14.054us 50 50 100.00
edn_disable_auto_req_mode 1.420s 44.660us 42 50 84.00
V2 stress_all edn_stress_all 6.870s 364.053us 50 50 100.00
V2 intr_test edn_intr_test 1.030s 23.276us 50 50 100.00
V2 alert_test edn_alert_test 1.140s 31.520us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.690s 754.289us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.690s 754.289us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.950s 19.790us 5 5 100.00
edn_csr_rw 1.000s 15.982us 20 20 100.00
edn_csr_aliasing 1.440s 46.231us 5 5 100.00
edn_same_csr_outstanding 1.470s 38.761us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.950s 19.790us 5 5 100.00
edn_csr_rw 1.000s 15.982us 20 20 100.00
edn_csr_aliasing 1.440s 46.231us 5 5 100.00
edn_same_csr_outstanding 1.470s 38.761us 20 20 100.00
V2 TOTAL 782 790 98.99
V2S tl_intg_err edn_sec_cm 10.640s 669.368us 5 5 100.00
edn_tl_intg_err 2.560s 101.697us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.990s 17.841us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.700s 421.997us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.640s 669.368us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.640s 669.368us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.640s 669.368us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.700s 421.997us 50 50 100.00
edn_sec_cm 10.640s 669.368us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.700s 421.997us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.560s 101.697us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 41.944m 235.811ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 972 980 99.18

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.11 98.27 93.63 96.84 83.24 96.87 96.58 93.35

Failure Buckets

Past Results