EDN Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	18.150us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	18.798us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	15.567us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.080s	795.179us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.550s	40.086us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.150s	61.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	15.567us	20	20	100.00
		edn_csr_aliasing	1.550s	40.086us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.518m	4.593ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.518m	4.593ms	300	300	100.00
V2	genbits	edn_genbits	1.518m	4.593ms	300	300	100.00
V2	interrupts	edn_intr	1.230s	21.677us	50	50	100.00
V2	alerts	edn_alert	1.380s	271.295us	50	50	100.00
V2	errs	edn_err	1.450s	40.280us	100	100	100.00
V2	disable	edn_disable	1.000s	22.894us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	47.332us	36	50	72.00
V2	stress_all	edn_stress_all	7.130s	366.471us	50	50	100.00
V2	intr_test	edn_intr_test	0.950s	55.387us	50	50	100.00
V2	alert_test	edn_alert_test	1.260s	72.394us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.040s	112.292us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.040s	112.292us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	18.798us	5	5	100.00
		edn_csr_rw	1.000s	15.567us	20	20	100.00
		edn_csr_aliasing	1.550s	40.086us	5	5	100.00
		edn_same_csr_outstanding	1.490s	38.974us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	18.798us	5	5	100.00
		edn_csr_rw	1.000s	15.567us	20	20	100.00
		edn_csr_aliasing	1.550s	40.086us	5	5	100.00
		edn_same_csr_outstanding	1.490s	38.974us	20	20	100.00
V2		TOTAL			776	790	98.23
V2S	tl_intg_err	edn_sec_cm	6.840s	3.662ms	5	5	100.00
		edn_tl_intg_err	5.720s	338.140us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.010s	16.476us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	271.295us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.840s	3.662ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.840s	3.662ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.840s	3.662ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	271.295us	50	50	100.00
		edn_sec_cm	6.840s	3.662ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	271.295us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.720s	338.140us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.163m	209.177ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			966	980	98.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.02	98.27	93.63	96.79	82.66	96.87	96.58	93.35

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 14 failures:
  • Test edn_disable_auto_req_mode has 14 failures.

    • 2.edn_disable_auto_req_mode.50602282477554861420801282622694523289141722661308564645789490227336854097975
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  21098915 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 11 [0xb]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  21098915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.edn_disable_auto_req_mode.104531706031904443422917085880337301266847184023272696963133172910860072457284
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  94937833 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  94937833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 12 more failures.

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