EDN Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.030s	14.453us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	24.625us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.240s	32.003us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.680s	1.009ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.640s	90.543us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.840s	26.411us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.240s	32.003us	20	20	100.00
		edn_csr_aliasing	1.640s	90.543us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.291m	4.507ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.291m	4.507ms	300	300	100.00
V2	genbits	edn_genbits	1.291m	4.507ms	300	300	100.00
V2	interrupts	edn_intr	1.260s	24.432us	50	50	100.00
V2	alerts	edn_alert	1.430s	213.471us	50	50	100.00
V2	errs	edn_err	1.430s	32.973us	100	100	100.00
V2	disable	edn_disable	0.970s	14.515us	50	50	100.00
		edn_disable_auto_req_mode	1.910s	52.551us	40	50	80.00
V2	stress_all	edn_stress_all	7.120s	359.617us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	19.958us	50	50	100.00
V2	alert_test	edn_alert_test	1.200s	62.151us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.530s	458.473us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.530s	458.473us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	24.625us	5	5	100.00
		edn_csr_rw	1.240s	32.003us	20	20	100.00
		edn_csr_aliasing	1.640s	90.543us	5	5	100.00
		edn_same_csr_outstanding	1.420s	35.341us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	24.625us	5	5	100.00
		edn_csr_rw	1.240s	32.003us	20	20	100.00
		edn_csr_aliasing	1.640s	90.543us	5	5	100.00
		edn_same_csr_outstanding	1.420s	35.341us	20	20	100.00
V2		TOTAL			780	790	98.73
V2S	tl_intg_err	edn_sec_cm	6.020s	350.685us	5	5	100.00
		edn_tl_intg_err	2.830s	115.818us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.030s	18.695us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.430s	213.471us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.020s	350.685us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.020s	350.685us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.020s	350.685us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.430s	213.471us	50	50	100.00
		edn_sec_cm	6.020s	350.685us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.430s	213.471us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.830s	115.818us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	55.783m	127.792ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			970	980	98.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.89	98.27	93.52	96.79	82.08	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 10 failures:
  • Test edn_disable_auto_req_mode has 10 failures.

    • 0.edn_disable_auto_req_mode.108010870859797482483945152246134227790537090722793282732270478898652455125932
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  30525416 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  30525416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.edn_disable_auto_req_mode.50988875537874760149651381793142307949118709185780814464266030689354119302282
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  29581019 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  29581019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

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