EDN Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: 4ee21f808f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.070s	45.990us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	111.810us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	29.993us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.750s	250.438us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.590s	94.081us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.780s	29.075us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	29.993us	20	20	100.00
		edn_csr_aliasing	1.590s	94.081us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.230m	2.293ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.230m	2.293ms	300	300	100.00
V2	genbits	edn_genbits	1.230m	2.293ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	19.700us	50	50	100.00
V2	alerts	edn_alert	1.370s	58.837us	50	50	100.00
V2	errs	edn_err	1.560s	33.555us	100	100	100.00
V2	disable	edn_disable	0.990s	11.676us	50	50	100.00
		edn_disable_auto_req_mode	1.520s	111.470us	43	50	86.00
V2	stress_all	edn_stress_all	7.260s	370.530us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	34.953us	50	50	100.00
V2	alert_test	edn_alert_test	1.290s	41.815us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.020s	1.163ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.020s	1.163ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	111.810us	5	5	100.00
		edn_csr_rw	0.960s	29.993us	20	20	100.00
		edn_csr_aliasing	1.590s	94.081us	5	5	100.00
		edn_same_csr_outstanding	1.600s	41.633us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	111.810us	5	5	100.00
		edn_csr_rw	0.960s	29.993us	20	20	100.00
		edn_csr_aliasing	1.590s	94.081us	5	5	100.00
		edn_same_csr_outstanding	1.600s	41.633us	20	20	100.00
V2		TOTAL			783	790	99.11
V2S	tl_intg_err	edn_sec_cm	7.300s	476.454us	5	5	100.00
		edn_tl_intg_err	4.000s	337.668us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.980s	40.687us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.370s	58.837us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.300s	476.454us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.300s	476.454us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.300s	476.454us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.370s	58.837us	50	50	100.00
		edn_sec_cm	7.300s	476.454us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.370s	58.837us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.000s	337.668us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.222h	2.640s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			973	980	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.88	98.27	93.64	96.79	82.08	96.87	96.58	92.95

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 7 failures:
  • Test edn_disable_auto_req_mode has 7 failures.

    • 2.edn_disable_auto_req_mode.61868885758842941225413460659985180128761837670321282973752298134897462392104
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  44863961 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  44863961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.edn_disable_auto_req_mode.113609746113476074729015898691141101802902150521211225159291846820745527612173
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  14690626 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  14690626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

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