EDN Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.659us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.930s	15.737us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.980s	26.006us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.960s	251.345us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.560s	152.182us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.930s	108.220us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.980s	26.006us	20	20	100.00
		edn_csr_aliasing	1.560s	152.182us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.837m	24.380ms	300	300	100.00
V2	csrng_commands	edn_genbits	3.837m	24.380ms	300	300	100.00
V2	genbits	edn_genbits	3.837m	24.380ms	300	300	100.00
V2	interrupts	edn_intr	1.220s	22.786us	50	50	100.00
V2	alerts	edn_alert	1.380s	255.031us	50	50	100.00
V2	errs	edn_err	1.490s	35.288us	100	100	100.00
V2	disable	edn_disable	0.970s	14.812us	50	50	100.00
		edn_disable_auto_req_mode	1.450s	96.652us	35	50	70.00
V2	stress_all	edn_stress_all	7.930s	390.963us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	61.348us	50	50	100.00
V2	alert_test	edn_alert_test	1.120s	167.243us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.860s	443.845us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.860s	443.845us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.930s	15.737us	5	5	100.00
		edn_csr_rw	0.980s	26.006us	20	20	100.00
		edn_csr_aliasing	1.560s	152.182us	5	5	100.00
		edn_same_csr_outstanding	1.440s	123.465us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.930s	15.737us	5	5	100.00
		edn_csr_rw	0.980s	26.006us	20	20	100.00
		edn_csr_aliasing	1.560s	152.182us	5	5	100.00
		edn_same_csr_outstanding	1.440s	123.465us	20	20	100.00
V2		TOTAL			775	790	98.10
V2S	tl_intg_err	edn_sec_cm	5.870s	712.404us	5	5	100.00
		edn_tl_intg_err	3.960s	189.704us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.040s	17.857us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	255.031us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.870s	712.404us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.870s	712.404us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.870s	712.404us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	255.031us	50	50	100.00
		edn_sec_cm	5.870s	712.404us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	255.031us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.960s	189.704us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	39.544m	106.125ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			965	980	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.75	98.27	93.64	96.84	80.92	96.87	96.58	93.15

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 15 failures:
  • Test edn_disable_auto_req_mode has 15 failures.

    • 0.edn_disable_auto_req_mode.72476828571795107576365400858024841875796430986652902529235153731513820419048
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  24858503 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (8 [0x8] vs 11 [0xb]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  24858503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.edn_disable_auto_req_mode.95377128294877121721813775513341535376390715659897590679614405926691867467277
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  34522628 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  34522628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

Past Results

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