EDN Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.979us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	62.619us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.950s	15.395us	19	20	95.00
V1	csr_bit_bash	edn_csr_bit_bash	5.900s	261.696us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.620s	43.629us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.730s	94.913us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.950s	15.395us	19	20	95.00
		edn_csr_aliasing	1.620s	43.629us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	firmware	edn_genbits	1.317m	2.902ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.317m	2.902ms	300	300	100.00
V2	genbits	edn_genbits	1.317m	2.902ms	300	300	100.00
V2	interrupts	edn_intr	1.320s	25.264us	50	50	100.00
V2	alerts	edn_alert	1.510s	321.007us	50	50	100.00
V2	errs	edn_err	1.360s	27.922us	100	100	100.00
V2	disable	edn_disable	0.990s	13.402us	50	50	100.00
		edn_disable_auto_req_mode	1.410s	41.826us	39	50	78.00
V2	stress_all	edn_stress_all	7.630s	489.910us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	12.478us	50	50	100.00
V2	alert_test	edn_alert_test	1.420s	86.452us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.580s	152.402us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.580s	152.402us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	62.619us	5	5	100.00
		edn_csr_rw	0.950s	15.395us	19	20	95.00
		edn_csr_aliasing	1.620s	43.629us	5	5	100.00
		edn_same_csr_outstanding	1.450s	171.332us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	62.619us	5	5	100.00
		edn_csr_rw	0.950s	15.395us	19	20	95.00
		edn_csr_aliasing	1.620s	43.629us	5	5	100.00
		edn_same_csr_outstanding	1.450s	171.332us	20	20	100.00
V2		TOTAL			779	790	98.61
V2S	tl_intg_err	edn_sec_cm	6.360s	1.504ms	5	5	100.00
		edn_tl_intg_err	3.090s	278.699us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.020s	18.201us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.510s	321.007us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.360s	1.504ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.360s	1.504ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.360s	1.504ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.510s	321.007us	50	50	100.00
		edn_sec_cm	6.360s	1.504ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.510s	321.007us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.090s	278.699us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	45.660m	483.804ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.94	98.27	93.71	96.74	82.08	96.87	96.58	93.35

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 11 failures:
- Test edn_disable_auto_req_mode has 11 failures.
  - 4.edn_disable_auto_req_mode.68882382592471418621983052861300034199292465373199850857346659961049706366563
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/4.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  24487375 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  24487375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.edn_disable_auto_req_mode.80730442512573901490868267802424663439883437591097248635194953125278020788492
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  28161338 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  28161338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test edn_csr_rw has 1 failures.

5.edn_csr_rw.30862233386268699202919264962039101943756079587854560202238445527889339757787
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_csr_rw/latest/run.log

  [make]: simulate
  cd /workspace/5.edn_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725445339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1725445339
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Apr  2 12:31 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255