2723ca659d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 1.060s | 19.065us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 1.000s | 20.584us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 0.980s | 14.560us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 5.250s | 182.884us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.590s | 209.382us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 2.010s | 51.632us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.980s | 14.560us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.590s | 209.382us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | firmware | edn_genbits | 1.757m | 9.880ms | 300 | 300 | 100.00 |
| V2 | csrng_commands | edn_genbits | 1.757m | 9.880ms | 300 | 300 | 100.00 |
| V2 | genbits | edn_genbits | 1.757m | 9.880ms | 300 | 300 | 100.00 |
| V2 | interrupts | edn_intr | 1.210s | 22.611us | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 1.400s | 123.276us | 50 | 50 | 100.00 |
| V2 | errs | edn_err | 1.380s | 31.570us | 100 | 100 | 100.00 |
| V2 | disable | edn_disable | 0.950s | 12.772us | 50 | 50 | 100.00 |
| edn_disable_auto_req_mode | 1.800s | 50.415us | 38 | 50 | 76.00 | ||
| V2 | stress_all | edn_stress_all | 7.230s | 375.327us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 0.930s | 14.928us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 1.080s | 42.395us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 3.840s | 508.480us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 3.840s | 508.480us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 1.000s | 20.584us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.980s | 14.560us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.590s | 209.382us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.560s | 41.937us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 1.000s | 20.584us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.980s | 14.560us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.590s | 209.382us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.560s | 41.937us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 778 | 790 | 98.48 | |||
| V2S | tl_intg_err | edn_sec_cm | 6.740s | 939.056us | 5 | 5 | 100.00 |
| edn_tl_intg_err | 2.560s | 107.890us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.050s | 18.801us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.400s | 123.276us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 6.740s | 939.056us | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 6.740s | 939.056us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 6.740s | 939.056us | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.400s | 123.276us | 50 | 50 | 100.00 |
| edn_sec_cm | 6.740s | 939.056us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.400s | 123.276us | 50 | 50 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 2.560s | 107.890us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 56.422m | 302.528ms | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 967 | 980 | 98.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 11 | 11 | 10 | 90.91 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.91 | 98.27 | 93.52 | 96.74 | 82.08 | 96.87 | 96.58 | 93.35 |
UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 12 failures:
0.edn_disable_auto_req_mode.88663033550084043229057755995271333418051180899731423085613297942413169294238
Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 148840655 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 148840655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.edn_disable_auto_req_mode.46290148664534676031725370589474834349698547659448225149097709585038442791246
Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log
UVM_ERROR @ 14298696 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
UVM_INFO @ 14298696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
6.edn_stress_all_with_rand_reset.11464367556325793933517675613713967888441382832034848530673415642795223553284
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e039038d-3ebc-47c3-8551-6acb14609b96