7773b039d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 20 | 0.00 | ||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | firmware | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | csrng_commands | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | genbits | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | interrupts | edn_intr | 0 | 50 | 0.00 | ||
| V2 | alerts | edn_alert | 0 | 50 | 0.00 | ||
| V2 | errs | edn_err | 0 | 100 | 0.00 | ||
| V2 | disable | edn_disable | 0 | 50 | 0.00 | ||
| edn_disable_auto_req_mode | 0 | 50 | 0.00 | ||||
| V2 | stress_all | edn_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | edn_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 790 | 0.00 | |||
| V2S | tl_intg_err | edn_sec_cm | 0 | 5 | 0.00 | ||
| edn_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 0 | 10 | 0.00 | ||
| V2S | sec_cm_config_mubi | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0 | 50 | 0.00 | ||
| edn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 35 | 0.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 980 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 980 failures:
0.edn_smoke.70339111930194417905116024973934253782843853729590848799819173023202889359932
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_smoke/latest/run.log
1.edn_smoke.37008574179566408341643401915347107105503084463179080487489295650444067329299
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_smoke/latest/run.log
... and 48 more failures.
0.edn_regwen.54992595927596760436411557966873681151079123717513559439474992617263004194195
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_regwen/latest/run.log
1.edn_regwen.39928132269196758026110281484130584279473046701362892686573610112315039371418
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest/run.log
... and 8 more failures.
0.edn_genbits.29624949337754532736902081041082756423531282295404485665629002038412521461437
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_genbits/latest/run.log
1.edn_genbits.47924461539177674472760717117774273004674761735845151377304662537182265765992
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest/run.log
... and 298 more failures.
0.edn_stress_all.38599546543034515873330684859673853821802293158590632960520510403434472273665
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest/run.log
1.edn_stress_all.78479617905670182150614090029430446718388873905398538237962277630456381600745
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest/run.log
... and 48 more failures.
0.edn_stress_all_with_rand_reset.106793843875156611182185007905565473511572500025813235136860709910094049750635
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
1.edn_stress_all_with_rand_reset.70985777228269278899627360047497075535651513168963921126245656142441848824735
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/cov_report/cov_report.log