EDN Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: 7773b039d0

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0 50 0.00
V1 csr_hw_reset edn_csr_hw_reset 0 5 0.00
V1 csr_rw edn_csr_rw 0 20 0.00
V1 csr_bit_bash edn_csr_bit_bash 0 5 0.00
V1 csr_aliasing edn_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0 20 0.00
edn_csr_aliasing 0 5 0.00
V1 TOTAL 0 105 0.00
V2 firmware edn_genbits 0 300 0.00
V2 csrng_commands edn_genbits 0 300 0.00
V2 genbits edn_genbits 0 300 0.00
V2 interrupts edn_intr 0 50 0.00
V2 alerts edn_alert 0 50 0.00
V2 errs edn_err 0 100 0.00
V2 disable edn_disable 0 50 0.00
edn_disable_auto_req_mode 0 50 0.00
V2 stress_all edn_stress_all 0 50 0.00
V2 intr_test edn_intr_test 0 50 0.00
V2 alert_test edn_alert_test 0 50 0.00
V2 tl_d_oob_addr_access edn_tl_errors 0 20 0.00
V2 tl_d_illegal_access edn_tl_errors 0 20 0.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0 5 0.00
edn_csr_rw 0 20 0.00
edn_csr_aliasing 0 5 0.00
edn_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access edn_csr_hw_reset 0 5 0.00
edn_csr_rw 0 20 0.00
edn_csr_aliasing 0 5 0.00
edn_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 790 0.00
V2S tl_intg_err edn_sec_cm 0 5 0.00
edn_tl_intg_err 0 20 0.00
V2S sec_cm_config_regwen edn_regwen 0 10 0.00
V2S sec_cm_config_mubi edn_alert 0 50 0.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 0 5 0.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 0 5 0.00
V2S sec_cm_ctr_redun edn_sec_cm 0 5 0.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0 50 0.00
edn_sec_cm 0 5 0.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0 50 0.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 0 20 0.00
V2S TOTAL 0 35 0.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 0 980 0.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 0 0.00
V2 11 11 0 0.00
V2S 3 3 0 0.00
V3 1 1 0 0.00

Failure Buckets

Past Results