1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | edn_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | edn_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | edn_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0 | 20 | 0.00 | ||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | firmware | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | csrng_commands | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | genbits | edn_genbits | 0 | 300 | 0.00 | ||
| V2 | interrupts | edn_intr | 0 | 50 | 0.00 | ||
| V2 | alerts | edn_alert | 0 | 50 | 0.00 | ||
| V2 | errs | edn_err | 0 | 100 | 0.00 | ||
| V2 | disable | edn_disable | 0 | 50 | 0.00 | ||
| edn_disable_auto_req_mode | 0 | 50 | 0.00 | ||||
| V2 | stress_all | edn_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | edn_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | edn_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | edn_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0 | 5 | 0.00 | ||
| edn_csr_rw | 0 | 20 | 0.00 | ||||
| edn_csr_aliasing | 0 | 5 | 0.00 | ||||
| edn_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 790 | 0.00 | |||
| V2S | tl_intg_err | edn_sec_cm | 0 | 5 | 0.00 | ||
| edn_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_config_regwen | edn_regwen | 0 | 10 | 0.00 | ||
| V2S | sec_cm_config_mubi | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | edn_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 0 | 50 | 0.00 | ||
| edn_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 0 | 50 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 35 | 0.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 980 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 11 | 11 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 980 failures:
0.edn_smoke.58079694434190929769437817892687561701093349652079139766230271547724527047611
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_smoke/latest/run.log
1.edn_smoke.7858827821340557153305371633264061017410027104045552599146462694217001978275
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_smoke/latest/run.log
... and 48 more failures.
0.edn_regwen.30570144825844534070430888212535950019427364832736873176748640428937886965276
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_regwen/latest/run.log
1.edn_regwen.35591010705605012990153773253934809197834532689405231893363845855347864870494
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_regwen/latest/run.log
... and 8 more failures.
0.edn_genbits.35838925242268213368163456097061161064445744118479330140645618362122598109532
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_genbits/latest/run.log
1.edn_genbits.28296733019872443440719354238665553379064358576494317964968344350954513150901
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest/run.log
... and 298 more failures.
0.edn_stress_all.16252465579876125119429018329976019028413729887171757113743446246799294810450
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all/latest/run.log
1.edn_stress_all.83514011681972051055445182406515381907540336667747144356187755175282610737108
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest/run.log
... and 48 more failures.
0.edn_stress_all_with_rand_reset.60251656673043700322488947310101666395880773437812848313257810313554795082792
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
1.edn_stress_all_with_rand_reset.15120814535134476015895633191262364066101756176937956888031819966300667298521
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/cov_report/cov_report.log