EDN Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	18.567us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	16.873us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	14.748us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.750s	694.985us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.310s	20.981us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.140s	257.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	14.748us	20	20	100.00
		edn_csr_aliasing	1.310s	20.981us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.130s	491.435us	300	300	100.00
V2	csrng_commands	edn_genbits	4.130s	491.435us	300	300	100.00
V2	genbits	edn_genbits	4.130s	491.435us	300	300	100.00
V2	interrupts	edn_intr	1.240s	20.767us	50	50	100.00
V2	alerts	edn_alert	1.390s	106.786us	50	50	100.00
V2	errs	edn_err	1.280s	28.536us	100	100	100.00
V2	disable	edn_disable	6.200s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.560s	46.097us	40	50	80.00
V2	stress_all	edn_stress_all	6.960s	394.626us	50	50	100.00
V2	intr_test	edn_intr_test	1.040s	238.439us	50	50	100.00
V2	alert_test	edn_alert_test	2.160s	108.289us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.210s	555.397us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.210s	555.397us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	16.873us	5	5	100.00
		edn_csr_rw	1.000s	14.748us	20	20	100.00
		edn_csr_aliasing	1.310s	20.981us	5	5	100.00
		edn_same_csr_outstanding	1.470s	44.600us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	16.873us	5	5	100.00
		edn_csr_rw	1.000s	14.748us	20	20	100.00
		edn_csr_aliasing	1.310s	20.981us	5	5	100.00
		edn_same_csr_outstanding	1.470s	44.600us	20	20	100.00
V2		TOTAL			779	790	98.61
V2S	tl_intg_err	edn_sec_cm	2.452m	10.375ms	4	5	80.00
		edn_tl_intg_err	10.110s	686.074us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.960s	16.874us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.390s	106.786us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.452m	10.375ms	4	5	80.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.452m	10.375ms	4	5	80.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.452m	10.375ms	4	5	80.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.390s	106.786us	50	50	100.00
		edn_sec_cm	2.452m	10.375ms	4	5	80.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.390s	106.786us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	10.110s	686.074us	20	20	100.00
V2S		TOTAL			34	35	97.14
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	51.789m	1.137s	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			968	980	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	2	66.67
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.07	98.27	93.71	96.79	83.82	96.87	96.58	92.46

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 10 failures:
- Test edn_disable_auto_req_mode has 10 failures.
  - 5.edn_disable_auto_req_mode.38776371937201157120922044582955677458538515105188383470080629147078811879732
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  34709320 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  34709320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.edn_disable_auto_req_mode.107186272689576369288142507263405125772270122805714814474761921080386926147941
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  32346157 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  32346157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (cip_base_vseq.sv:636) [edn_common_vseq] timeout wait for alert handshake:fatal_alert has 1 failures:
- Test edn_sec_cm has 1 failures.
  - 0.edn_sec_cm.17339107713405566977197673294010277882116719395986133206782532501609346172771
    Line 473, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log
```
  UVM_FATAL @ 10374520299 ps: (cip_base_vseq.sv:636) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] timeout wait for alert handshake:fatal_alert
  UVM_INFO @ 10374520299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable has 1 failures.
  - 14.edn_disable.76446759638886231305750486539270465475336559037374236197259240455511255627291
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f4903e77a`