EDN Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.020s 18.639us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.970s 60.089us 5 5 100.00
V1 csr_rw edn_csr_rw 0.940s 15.257us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.850s 177.198us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.550s 74.954us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.960s 29.890us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.940s 15.257us 20 20 100.00
edn_csr_aliasing 1.550s 74.954us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.226m 10.462ms 300 300 100.00
V2 csrng_commands edn_genbits 2.226m 10.462ms 300 300 100.00
V2 genbits edn_genbits 2.226m 10.462ms 300 300 100.00
V2 interrupts edn_intr 1.220s 24.918us 50 50 100.00
V2 alerts edn_alert 1.410s 277.388us 50 50 100.00
V2 errs edn_err 1.410s 34.165us 100 100 100.00
V2 disable edn_disable 0.950s 13.710us 50 50 100.00
edn_disable_auto_req_mode 1.400s 50.109us 38 50 76.00
V2 stress_all edn_stress_all 7.170s 396.054us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 12.493us 50 50 100.00
V2 alert_test edn_alert_test 1.650s 66.825us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.100s 110.510us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.100s 110.510us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.970s 60.089us 5 5 100.00
edn_csr_rw 0.940s 15.257us 20 20 100.00
edn_csr_aliasing 1.550s 74.954us 5 5 100.00
edn_same_csr_outstanding 1.450s 106.495us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.970s 60.089us 5 5 100.00
edn_csr_rw 0.940s 15.257us 20 20 100.00
edn_csr_aliasing 1.550s 74.954us 5 5 100.00
edn_same_csr_outstanding 1.450s 106.495us 20 20 100.00
V2 TOTAL 778 790 98.48
V2S tl_intg_err edn_sec_cm 8.760s 1.565ms 5 5 100.00
edn_tl_intg_err 4.860s 266.978us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.970s 30.335us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 277.388us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.760s 1.565ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.760s 1.565ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.760s 1.565ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 277.388us 50 50 100.00
edn_sec_cm 8.760s 1.565ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 277.388us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.860s 266.978us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 43.075m 1.671s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 968 980 98.78

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.66 98.27 93.71 96.79 80.92 96.87 96.58 92.46

Failure Buckets

Past Results