EDN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	18.919us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	58.712us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	15.998us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.160s	175.770us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.610s	82.631us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.810s	31.863us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	15.998us	20	20	100.00
		edn_csr_aliasing	1.610s	82.631us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.010s	274.887us	300	300	100.00
V2	csrng_commands	edn_genbits	4.010s	274.887us	300	300	100.00
V2	genbits	edn_genbits	4.010s	274.887us	300	300	100.00
V2	interrupts	edn_intr	1.220s	21.296us	50	50	100.00
V2	alerts	edn_alert	1.590s	374.469us	50	50	100.00
V2	errs	edn_err	1.370s	35.667us	100	100	100.00
V2	disable	edn_disable	0.980s	14.047us	50	50	100.00
		edn_disable_auto_req_mode	2.800s	500.000us	41	50	82.00
V2	stress_all	edn_stress_all	6.040s	305.677us	50	50	100.00
V2	intr_test	edn_intr_test	0.970s	17.398us	50	50	100.00
V2	alert_test	edn_alert_test	2.130s	105.678us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.640s	120.840us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.640s	120.840us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	58.712us	5	5	100.00
		edn_csr_rw	0.960s	15.998us	20	20	100.00
		edn_csr_aliasing	1.610s	82.631us	5	5	100.00
		edn_same_csr_outstanding	1.630s	543.712us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	58.712us	5	5	100.00
		edn_csr_rw	0.960s	15.998us	20	20	100.00
		edn_csr_aliasing	1.610s	82.631us	5	5	100.00
		edn_same_csr_outstanding	1.630s	543.712us	20	20	100.00
V2		TOTAL			781	790	98.86
V2S	tl_intg_err	edn_sec_cm	6.550s	3.144ms	5	5	100.00
		edn_tl_intg_err	7.780s	1.912ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.030s	29.020us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.590s	374.469us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.550s	3.144ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.550s	3.144ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.550s	3.144ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.590s	374.469us	50	50	100.00
		edn_sec_cm	6.550s	3.144ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.590s	374.469us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	7.780s	1.912ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	52.787m	734.755ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			971	980	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.06	98.27	93.71	96.79	80.35	96.87	99.77	92.65

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 8 failures:
- Test edn_disable_auto_req_mode has 8 failures.
  - 7.edn_disable_auto_req_mode.13539781647055210951985671496803488966827032668339162871373450940279989080082
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  41618572 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  41618572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.edn_disable_auto_req_mode.39177525517071215449274790650016290531431751626902521871616939515858623511067
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  13271140 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  13271140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 45.edn_disable_auto_req_mode.57234580761932533249352914200287956971132351808973972498803135342537937844280
    Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d3942ca074`