EDN Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.090s	19.380us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.010s	21.853us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.020s	15.069us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.170s	944.810us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.710s	82.267us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.750s	99.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.020s	15.069us	20	20	100.00
		edn_csr_aliasing	1.710s	82.267us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.921m	8.104ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.921m	8.104ms	300	300	100.00
V2	genbits	edn_genbits	1.921m	8.104ms	300	300	100.00
V2	interrupts	edn_intr	1.170s	21.992us	50	50	100.00
V2	alerts	edn_alert	1.430s	224.470us	50	50	100.00
V2	errs	edn_err	1.380s	29.727us	100	100	100.00
V2	disable	edn_disable	0.930s	14.096us	50	50	100.00
		edn_disable_auto_req_mode	1.410s	51.977us	39	50	78.00
V2	stress_all	edn_stress_all	7.200s	378.172us	50	50	100.00
V2	intr_test	edn_intr_test	0.990s	20.743us	50	50	100.00
V2	alert_test	edn_alert_test	1.090s	86.872us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.920s	940.059us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.920s	940.059us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.010s	21.853us	5	5	100.00
		edn_csr_rw	1.020s	15.069us	20	20	100.00
		edn_csr_aliasing	1.710s	82.267us	5	5	100.00
		edn_same_csr_outstanding	1.470s	82.709us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.010s	21.853us	5	5	100.00
		edn_csr_rw	1.020s	15.069us	20	20	100.00
		edn_csr_aliasing	1.710s	82.267us	5	5	100.00
		edn_same_csr_outstanding	1.470s	82.709us	20	20	100.00
V2		TOTAL			779	790	98.61
V2S	tl_intg_err	edn_sec_cm	10.020s	1.741ms	5	5	100.00
		edn_tl_intg_err	2.670s	104.388us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	51.834us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.430s	224.470us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.020s	1.741ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.020s	1.741ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.020s	1.741ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.020s	1.741ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.430s	224.470us	50	50	100.00
		edn_sec_cm	10.020s	1.741ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.430s	224.470us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.670s	104.388us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	41.761m	210.961ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			969	980	98.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.17	98.24	93.82	97.01	80.92	96.76	99.77	92.64

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 11 failures:
  • Test edn_disable_auto_req_mode has 11 failures.

    • 2.edn_disable_auto_req_mode.45041360574601090999333974960606146773135081085512340223523960088196725042972
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/2.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  53450923 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  53450923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.edn_disable_auto_req_mode.78835952897475372848929624578502629598329455901052975180587981873171805207518
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  13959584 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  13959584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

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