EDN Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	17.208us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.990s	17.521us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.030s	17.313us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.320s	353.325us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.250s	34.532us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.590s	65.738us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.030s	17.313us	20	20	100.00
		edn_csr_aliasing	1.250s	34.532us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.400s	336.825us	300	300	100.00
V2	csrng_commands	edn_genbits	4.400s	336.825us	300	300	100.00
V2	genbits	edn_genbits	4.400s	336.825us	300	300	100.00
V2	interrupts	edn_intr	1.240s	22.477us	50	50	100.00
V2	alerts	edn_alert	1.710s	363.001us	50	50	100.00
V2	errs	edn_err	1.520s	46.922us	100	100	100.00
V2	disable	edn_disable	1.010s	33.879us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	40.528us	46	50	92.00
V2	stress_all	edn_stress_all	7.510s	382.780us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	17.058us	50	50	100.00
V2	alert_test	edn_alert_test	1.140s	28.444us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.850s	350.106us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.850s	350.106us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.990s	17.521us	5	5	100.00
		edn_csr_rw	1.030s	17.313us	20	20	100.00
		edn_csr_aliasing	1.250s	34.532us	5	5	100.00
		edn_same_csr_outstanding	1.570s	41.403us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.990s	17.521us	5	5	100.00
		edn_csr_rw	1.030s	17.313us	20	20	100.00
		edn_csr_aliasing	1.250s	34.532us	5	5	100.00
		edn_same_csr_outstanding	1.570s	41.403us	20	20	100.00
V2		TOTAL			786	790	99.49
V2S	tl_intg_err	edn_sec_cm	9.430s	1.238ms	5	5	100.00
		edn_tl_intg_err	3.520s	673.590us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.070s	18.023us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.710s	363.001us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.430s	1.238ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.430s	1.238ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.430s	1.238ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.430s	1.238ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.710s	363.001us	50	50	100.00
		edn_sec_cm	9.430s	1.238ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.710s	363.001us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.520s	673.590us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.061h	301.648ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			975	980	99.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.41	98.24	93.82	97.01	82.66	96.76	99.77	92.64

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 3 failures:
- Test edn_disable_auto_req_mode has 3 failures.
  - 19.edn_disable_auto_req_mode.7459750826809687364225781453612017776565884548093597923154499446554169744564
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  40400363 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  40400363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.edn_disable_auto_req_mode.74316712537537023578022160902957655406204555504089855529152301037620697182959
    Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/32.edn_disable_auto_req_mode/latest/run.log
```
  UVM_ERROR @  15024437 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
  UVM_INFO @  15024437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 20.edn_stress_all_with_rand_reset.19309296618436151061004537241108808860941343128781220282556340873839114718841
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/20.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:40d1c343-fc10-470d-90f1-1fa28c0caaab
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 33.edn_disable_auto_req_mode.115201018725288863593221056540592769198958657263108999485886516902863193855
    Line 263, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/33.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `41bc3e0c7f`