EDN Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.110s	18.560us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.020s	21.079us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	13.520us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.160s	261.336us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.640s	63.851us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.910s	30.293us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	13.520us	20	20	100.00
		edn_csr_aliasing	1.640s	63.851us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	5.310s	914.563us	300	300	100.00
V2	csrng_commands	edn_genbits	5.310s	914.563us	300	300	100.00
V2	genbits	edn_genbits	5.310s	914.563us	300	300	100.00
V2	interrupts	edn_intr	1.270s	20.449us	50	50	100.00
V2	alerts	edn_alert	1.380s	29.952us	50	50	100.00
V2	errs	edn_err	1.490s	37.368us	100	100	100.00
V2	disable	edn_disable	1.060s	19.347us	50	50	100.00
		edn_disable_auto_req_mode	1.430s	57.110us	45	50	90.00
V2	stress_all	edn_stress_all	7.580s	376.766us	50	50	100.00
V2	intr_test	edn_intr_test	0.930s	28.061us	50	50	100.00
V2	alert_test	edn_alert_test	1.060s	37.117us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.350s	1.366ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.350s	1.366ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.020s	21.079us	5	5	100.00
		edn_csr_rw	1.000s	13.520us	20	20	100.00
		edn_csr_aliasing	1.640s	63.851us	5	5	100.00
		edn_same_csr_outstanding	1.400s	59.751us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.020s	21.079us	5	5	100.00
		edn_csr_rw	1.000s	13.520us	20	20	100.00
		edn_csr_aliasing	1.640s	63.851us	5	5	100.00
		edn_same_csr_outstanding	1.400s	59.751us	20	20	100.00
V2		TOTAL			785	790	99.37
V2S	tl_intg_err	edn_sec_cm	7.860s	1.901ms	5	5	100.00
		edn_tl_intg_err	3.400s	191.161us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.040s	15.281us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.380s	29.952us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.860s	1.901ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.860s	1.901ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.860s	1.901ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.860s	1.901ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.380s	29.952us	50	50	100.00
		edn_sec_cm	7.860s	1.901ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.380s	29.952us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.400s	191.161us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	36.867m	434.912ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			975	980	99.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.50	98.24	93.64	91.35	82.08	96.76	99.77	92.64

Failure Buckets

• UVM_ERROR (edn_scoreboard.sv:313) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts has 5 failures:
  • Test edn_disable_auto_req_mode has 5 failures.

    • 14.edn_disable_auto_req_mode.25073709677499618650235236852309214987282840039974603589313103177326323862503
      Line 258, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/14.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  26602156 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (0 [0x0] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  26602156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.edn_disable_auto_req_mode.8829256851665771554595206219492407386130795133950756251731992219983574918194
      Line 261, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/23.edn_disable_auto_req_mode/latest/run.log

        UVM_ERROR @  23683633 ps: (edn_scoreboard.sv:313) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (4 [0x4] vs 7 [0x7]) reg name: edn_reg_block.sw_cmd_sts
        UVM_INFO @  23683633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

Past Results

• Latest
• lint
• 2024.04.24_07.51.02
• 2024.04.22_07.13.30
• 2024.04.19_04.54.54
• 2024.04.17_05.00.48
• 2024.04.16_04.06.54
• 2024.04.12_19.12.37